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dual , 14 - b it, 1230 msps, txdac+ digital - to - analog converter data sheet AD9121 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may resu lt from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. on e technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. techni cal sup port www.analog.com f eatures flexible lvds interface allows word or byte load single - carrier w - cdma aclr = 8 2 dbc at 1 22.88 mhz if analog output: adjustable 8.7 ma to 31.7 ma, r l = 25 to 50 integrated 2 /4 /8 interpolator/complex modulator allows carrier placement anywh ere in the dac bandwidth gain , dc offset, and phase adjustment for sideband suppression multiple chip synchronization interface s high performance, low noise pll clock multiplier digital inverse sinc filter low power: 1.5 w at 1.2 gsps, 800 mw at 500 msps, full operating conditions 72- lead, exposed paddle lfcsp applications wireless infrastructure w - cdma, cdma2000, td - scdma, wi max , gsm , lte digital high or low if synthesis transmit diversity wideband communications: lmds/mmds, point - to - point general descrip tion the AD9121 is a dual , 14- bit , high dynamic ran ge digital - to - analog converter (dac ) that provide s a sample rate of 123 0 m sps, permitting multicarrier generation up to the nyquist frequency. the AD9121 txdac+? include s features optimized for direct con version transmit applications, including complex digital mod - ulation , and gain and offset compensation. the dac outputs are optimized to interface seamlessly with analog quadrature modulators , such as the adl537x f - mod series from analog devices, inc. a 4 - wire serial port interface provides for program - ming/readback of many internal parameters. full - scale output current can be programmed over a range of 8. 7 ma to 31 .7 ma. the AD9121 comes in a 72 - lead lfcsp . produ ct highlights 1. ultralow noise and intermodulation distortion (imd) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies (if) . 2. p roprietary dac output switching technique enhances dynamic performance. 3. c urrent output s are easily configured for various single - ended or differential circuit topologies. 4. flexible lvds digital i nterface allows the standard 28- wire bus to be reduced to one - half of the width. companion products iq modulators: adl5370 , adl537x family iq modulators with pll and vco: adrf6701 , adrf670 x family clock drivers: ad9516 , ad951x family voltage regulator design tool: adisimpower typical signal chain notes 1. aqm = analog quadr a ture modul a t or. complex baseband dc complex if f if rf lo ? f if digi t a l baseband processor p a i dac q dac 2 2 2/4 2/4 antialiasing fi l ter aqm lo sin cos 09988-001 AD9121 figure 1 .
AD9121 data sheet rev. b | page 2 of 60 table of contents features .....................................................................................1 applications ...............................................................................1 general descript ion ..................................................................1 product highlights ....................................................................1 companion products ................................................................. 1 typical signal c hain ..................................................................1 revision history ........................................................................3 functional block diagram .........................................................4 specificati ons .............................................................................5 dc specifications ...................................................................5 digital specifications .............................................................6 digital input data timing specifications ...............................6 ac specifications ...................................................................7 absolute maximum ratings ......................................................8 thermal resistance ................................................................8 esd caution ..........................................................................8 pin configuration and function descriptions ...........................9 typical performance characteristics .......................................11 terminology ............................................................................17 theory of operation ................................................................18 serial port operation ...........................................................18 data format .........................................................................18 serial port pin descriptions .................................................18 serial port options ...............................................................19 device configuration register map and descriptions .........20 lvds input data ports ............................................................31 word interface mode ...........................................................31 byte interface mode .............................................................31 interface timing ..................................................................31 recommended frame input bias circuitry .........................32 fifo operation ...................................................................32 digital datapath ......................................................................36 premodulation .....................................................................36 interpolation filters .............................................................36 nco modulation ................................................................. 39 datapath configuration .......................................................39 determining interpolation filter modes ..............................40 datapath configuration examples .......................................41 data rates vs. interpolation modes .....................................42 coarse modul ation mixing sequences ................................ 42 quadrature phase correction .............................................. 43 dc offset correction .......................................................... 43 inverse sinc filter ................................................................ 43 dac input clock configurations ............................................ 44 driving the dacclk and refclk inputs ......................... 44 direct clocking ................................................................... 44 clock multiplication ............................................................ 44 pll settings ......................................................................... 45 configuring the vco tuning band ..................................... 45 analog outputs ....................................................................... 46 transmit dac operation .................................................... 46 auxiliary dac operation .................................................... 47 interfacing to modulators .................................................... 48 baseband fil ter implementation .......................................... 48 driving the adl5375 - 15 ..................................................... 48 reducing lo leakage and unwanted sidebands ................. 49 device power management ..................................................... 50 power dissipation ................................................................ 50 temperature sensor ............................................................. 51 multichip synchronization ...................................................... 52 s ynchronization with c lock multiplication ............................ 52 synchronization wi th direct clocking ................................. 53 data rate mode synchronization ........................................ 53 fifo rate mode synch ronization ....................................... 54 additional synchronization features ................................... 55 interrupt request operation ................................................... 56 interrupt service routine .................................................... 56 interface timing validation .................................................... 57 sed operation .................................................................... 57 sed example ....................................................................... 58 example start - up routine ....................................................... 59 device configuration .......................................................... 59 derived pll sett ings ........................................................... 59 derived nco settings ......................................................... 59 start - up sequence ............................................................... 59 outline dim ensions ................................................................ 60 ordering guide ................................................................... 60
data sheet AD9121 rev. b | page 3 of 60 revision history 10/12rev. 0 to rev. b updated outline dimensions ........................................................ 60
AD9121 data sheet rev. b | page 4 of 60 functional block dia gram mu l tichi p synchroniz a tion d13p/d13n d0p/d0n d at a receiver fifo hb1 hb2 hb3 nco and mod f d at a /2 pre mod hb1_clk mode hb2_clk hb3_clk int p f ac t or phase correction interna l clock timing and contro l logic 14 14 10 14 14 i offset q offset inv sinc aux 1.2g dac 1 14-bit iout1 p iout1n aux 1.2g dac 2 14-bit iout2 p iout2n ref and bias fsadj dacclk p dacclkn refclk p refclkn refio 10 gain 1 10 gain 2 dac_clk seria l input/output port programming registers power-on reset sdo sdio sclk cs reset irq 0 1 clock mu l tiplier (2 t o 16) clk rcvr clk rcvr pl l contro l sync dac clk_se l dac_clk pll_lock dci frame invsinc_clk 09988-002 AD9121 figure 2 .
data sheet AD9121 rev. b | page 5 of 60 specific ations dc specifications t min to t max , avdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i f s = 20 ma, maximum sample rate, unless otherwise noted. table 1. parameter min typ max unit resolution 14 bits accuracy differentia l nonlinearity (dnl) 0.5 lsb integral nonlinearity (inl) 1.0 lsb main dac outputs offset error ?0.001 0 +0.001 % fsr gain error (with internal reference) ? 3.6 2 +3.6 % fsr ful l - scale output current 1 8.66 19.6 31.66 ma output compliance ran ge ?1.0 +1.0 v power supply rejection ratio, avdd33 ?0.3 +0.3 % fsr/v output resistance 10 m gain dac monotonicity guaranteed settling time to w ithin 0.5 lsb 20 n s main dac temperature drift offset 0.04 ppm/ c gain 100 ppm/ c ref erence voltage 30 ppm/ c reference internal reference voltage 1.2 v output resistance 5 k analog supply voltages avdd33 3.13 3.3 3.47 v cvdd18 1.71 1.8 1.89 v digital supply voltages dvdd18 1.71 1.8 1.89 v iovdd 1.71 1.8/3.3 3.4 7 v power consumption 2 mode, f dac = 491.22 msps, if = 10 mhz, pll off 834 mw 2 mode, f dac = 491.22 msps, if = 10 mhz, pll on 913 mw 8 mode, f dac = 800 msps, if = 10 mhz , pll o ff 1135 1241 mw avdd33 55 57 ma cvdd18 85 90 ma dvdd18 444 495 ma power - down mode (register 0x01 = 0xf 0 ) 6.5 18 .8 mw power - up time 260 ms operating range ?40 +25 +85 c 1 based on a 10 k external resistor b etween fsadj and avss.
AD9121 data sheet rev. b | page 6 of 60 digital specificatio ns t min to t max , avdd33 = 3.3 v, i o v d d = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i f s = 20 ma, maximum sampl e rate, unless otherwise noted. table 2. parameter test conditions /comments min typ ma x unit cmos input logic level input v in logic high iovdd = 1.8 v 1.2 v iovdd = 2.5 v 1.6 v iovdd = 3.3 v 2.0 v input v in logic low iovdd = 1.8 v 0.6 v iovdd = 2.5 v, 3.3 v 0.8 v cmos output logic level output v out logic high iovdd = 1.8 v 1.4 v iovdd = 2.5 v 1.8 v iovdd = 3.3 v 2.4 v output v out logic low iovdd = 1.8 v, 2.5 v, 3.3 v 0.4 v lvds receiver inputs 1 applies to data , dci, and frame i nputs input voltage range, v ia or v ib 825 1675 mv input differe ntial threshold, v idth ?100 +100 mv input differential hysteresis, v idthh to v idthl 20 mv receiver differential input impedance, r in 80 120 lvds input rate see table 5 dac clock input (dacclkp, da cclkn) differential peak - to - peak voltage 100 500 2000 mv common - mode voltage self - biased input, ac - c ouple d 1.25 v maximum clock rate 12 3 0 mhz refclk input (refclkp, refclkn) differential peak - to - peak voltage 100 500 2000 mv common - mode voltage 1.25 v refclk frequency (pll mode) 1 ghz f vco 2.1 ghz 15.625 600 mhz refclk frequency (sync mode) se e th e multichip synchronization section for conditions 0 600 mhz serial p ort i nterfac e maximum clock rate (sclk) 40 mhz minimum pul se width high (t pwh ) 12.5 ns minimum pulse width low (t pw l ) 12.5 ns setup time, sdi o to sclk (t ds ) 1.9 ns hold time, sdio to sclk (t dh ) 0.2 ns data valid, sdo to sclk (t dv ) 2.3 ns setup time, cs to sclk (t dcsb ) 1.4 ns 1 lvds receiver is compliant with the ieee 1596 reduced rang e link, unless otherwise noted. digital input data t iming specifications table 3. parameter value unit latency (dacclk cycles) 1 interpolation (with or without modulation) 64 cycles 2 interpolation (with or without modulation) 135 cycles 4 interpol ation (with or without modulation) 292 cycles 8 interpolation (with or without modulation) 608 cycles inverse sinc 20 cycles fine modulation 8 cycles
data sheet AD9121 rev. b | page 7 of 60 ac specifications t min to t max , avdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i f s = 20 ma, maximum sample rate, unless otherwise noted. table 4. parameter min typ max unit spurious - free dynamic range (sfdr) f dac = 100 msps, f out = 20 mhz 78 dbc f dac = 200 msps, f out = 50 mhz 80 dbc f dac = 400 msps, f out = 70 mhz 69 dbc f dac = 800 msps, f out = 70 mhz 72 dbc two - tone intermodulation distortion (imd) f dac = 200 msps, f out = 50 mhz 84 dbc f dac = 400 msps, f out = 60 mhz 86 dbc f dac = 400 msps, f out = 80 mhz 84 dbc f dac = 800 msps, f out = 100 mhz 81 d bc noise spectral density (nsd) , eight - tone, 500 khz tone spacing f dac = 200 msps, f out = 80 mhz ?1 62 dbm/hz f dac = 400 msps, f out = 80 mhz ?16 3 dbm/hz f dac = 800 msps, f out = 80 mhz ?16 4 dbm/hz w - cdma adjacent channel leakage ratio (aclr), single - carrier f dac = 491.52 msps, f out = 10 mhz 84 dbc f dac = 491.52 msps, f out = 122.88 mhz 8 2 dbc f dac = 983.04 msps, f out = 122.88 mhz 83 dbc w - cdma second aclr, single - carrier f dac = 491.52 msps, f out = 10 mhz 88 dbc f dac = 491.52 msps, f out = 122.88 mhz 86 dbc f dac = 983.04 msps, f out = 122.88 mhz 88 dbc table 5. maximum rate (msps) with dvdd and cvdd supply regulation bus width interpolation factor f i nte rface (msps) f dac (msps) dvdd18, cvdd18 = dvdd18, cvdd18 = 1.8 v 5% 1.8 v 2% 1.9 v 2% 1.8 v 5% 1.8 v 2% 1.9 v 2% byte (7 bits) 1 1100 1200 1230 275 300 307.5 2 1100 1200 1230 550 600 615 4 1100 1200 1230 1100 1200 1230 8 550 600 615 1100 1200 1230 word (14 bits) 1 1100 1200 1230 550 600 615 2 (hb1) 900 1000 1000 900 1000 1000 2 (hb2) 1100 1200 1230 1100 1200 1230 4 550 600 615 1100 1200 1230 8 275 300 307.5 1100 1200 1230
AD9121 data sheet rev. b | page 8 of 60 absolute maximum rat ings table 6. parameter rating avdd33 to avss, epad, cvss, dvss ?0.3 v to +3.6 v iovdd to avss, epad, cvss, dvss ?0.3 v to +3.6 v dvdd18, cvdd18 to avss, epad, cvss, dvss ?0.3 v to +2.1 v avss to epad, cvss, dvss ?0.3 v to +0.3 v epad to avss, cvss, dvss ?0.3 v to +0.3 v cvss to avss, epad, dvss ?0.3 v to +0.3 v dvss to avss, epad, cvss ?0.3 v to +0.3 v fsadj, refio, iout1p , iout1n, iout2p , iout2n to avss ?0.3 v to avdd33 + 0.3 v d[15:0]p , d[15:0]n, framep , framen, dcip , dcin to epad, dvss ?0.3 v to dvdd18 + 0.3 v dacclkp , dacclkn, refclkp , refclkn to cvss ?0.3 v to cvdd18 + 0.3 v reset , irq , cs , sclk, sdio, sdo to epad, dvss ?0.3 v to iovdd + 0.3 v junction temperature 125c storage temperature range ?65c to +150c stresses above those listed under ab solute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposu re to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the exposed pad (epad) of the 72 - lead lfcsp must be soldered to the ground plane (avss) . the epad provides an electrical , thermal , and mechanic al connection to the board. typical ja , jb , and jc values are specified for a 4 - layer board in still air. airflow increases heat dissipation , effectively reducing ja and jb . table 7 . thermal resistance package ja jb jc unit conditions 72 - lead lfcsp 20.7 10.9 1.1 c/w epad soldered to ground plane esd caution
data sheet AD9121 rev. b | page 9 of 60 pin configuration an d function description s 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 cvdd18 dacclk p dacclkn cvss frame p framen irq d13 p d13n nc iovdd dvdd18 d12 p d12n d 1 1 p d 1 1n 17 d10 p 18 d10n 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 d9 p d9n d8 p d8n d7 p d7n d6 p d6n dci p dcin dvdd18 dvss d5 p d5n d4 p d4n 35 d3 p 36 d3n 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 reset cs sclk sdio sdo dvdd18 nc nc nc/bytelsbn nc/bytelsb p dvss dvdd18 d0n d0 p d1n d1 p d2n d2 p 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 cvdd18 cvdd18 refclk p refclkn a vdd33 iout1 p iout1n a vdd33 a vss fsadj refio a vss a vdd33 iout2n iout2 p a vdd33 a vss nc pin 1 indic a t or AD9121 t o p view (not to scale) notes 1. exposed p ad (e p ad) must be soldered t o the ground plane ( a vss). the e p ad provides an electrical, thermal, and mechanica l connection t o the board. 2. pins labeled nc can be allowed t o flo a t , but it is better t o connect these pins t o ground. a void routing high speed signals through these pins because noise coupling m a y resu l t . 09988-003 figure 3 . pin configuration table 8 . pin function descriptio n s pin no. mnemonic description 1 cvdd18 1.8 v clock supply. supplies clock receivers, clock distribution, and pll circuitry. 2 dacclkp dac clock input, positive . 3 dacclkn dac clock input, negative . 4 cvss clock supply common. 5 framep frame input , p ositive . this pin must be tied to dvss if not used. 6 framen frame input , negative . this pin must be tied to dvdd18 if not used. 7 irq interrupt request. open - drain, active low output. connect an external pull - up to iovdd through a 10 k resistor . 8 d1 3 p data bit 1 3 (msb), positive . 9 d1 3 n data bit 1 3 (msb), negative . 10 nc this pin is not conne cted internally (see figure 3 ). 11 iovdd supply pin for serial port i/o pins , reset , and irq . 1.8 v to 3.3 v can be supplied to this pin. 12 dvdd18 1.8 v digital supply. supplies power to digital core and digital data ports. 13 d1 2 p data bit 12 , positive. 14 d1 2 n data bit 12 , negative. 15 d1 1 p data bit 11 , positive. 16 d1 1 n data bit 11 , negative. 17 d1 0 p data bit 10 , positive. 18 d1 0 n data bit 10 , negative. 19 d 9 p data bit 9 , positive. 20 d 9 n data bit 9 , negative. 21 d 8 p data bit 8 , positive. 22 d 8 n data bit 8 , negative.
AD9121 data sheet rev. b | page 10 of 60 pin no. mnemonic description 23 d 7 p data bit 7 , positive. 24 d 7 n data bit 7 , neg ative. 25 d 6 p data bit 6 , positive. 26 d 6 n data bit 6 , negative. 27 dcip data clock input, positive. 28 dcin data clock input, negative. 29 dvdd18 1.8 v digital supply. supplies power to digital core and digital data ports. 30 dvss digital common. 3 1 d 5 p data bit 5 , positive. 32 d 5 n data bit 5 , negative. 33 d 4 p data bit 4 , positive. 34 d 4 n data bit 4 , negative. 35 d 3 p data bit 3 , positive. 36 d 3 n data bit 3 , negative. 37 d 2 p data bit 2 , positive. 38 d 2 n data bit 2 , negative. 39 d 1 p data bit 1 , positive. 40 d 1 n data bit 1 , negative. 41 d 0 p data bit 0 , positive. 42 d 0 n data bit 0 , negative. 43 dvdd18 1.8 v digital supply. supplies power to digital core and digital data ports. 44 dvss digital common. 45 nc/bytelsbp this pin is not conne cted internally (see figure 3 ) in word mode. lsb positive (data bit 0) in byte mode. 46 nc/bytelsbn this pin is not conne cted internally (see figure 3 ) in word mode. lsb negative (data bit 0) in byte mode. 47 nc this pin is not conne cted internally (see figure 3 ). 48 nc this pin is not conne cted internally (see figure 3 ). 49 dvdd18 1.8 v digital supply. supplies power to digital core and digital data port s. 50 sdo serial port data output (cmos levels w ith respect to iovdd). 51 sdio serial port data input/output (cmos levels w ith respect to iovdd). 52 sclk serial port clock input (cmos levels w ith respect to iovdd). 53 cs serial port c hip select , active low (cmos levels w ith respect to iovdd). 54 reset reset, active low (cmos levels w ith respect to iovdd) . 55 nc this pin is not conne cted internally (see figure 3 ). 56 avss analog supply comm on. 57 avdd33 3.3 v analog supply. 58 iout2p q dac positive current output. 59 iout2n q dac negative current output. 60 avdd33 3.3 v analog supply. 61 avss analog supply common. 62 refio voltage reference. nominally 1.2 v output. should be decoupled to avss . 63 fsadj ful l - scale current output adjust. place a 10 k resistor from this pin to avss . 64 avss analog supply common. 65 avdd33 3.3 v analog supply. 66 iout1n i dac nega tive current output. 67 iout1p i dac posi tive current output. 68 avdd33 3.3 v analog supply. 69 refclkn pll reference clock input , negative. this pin has a secondary function as a synchronization input. 70 refclkp pll reference clock input , positive. this pin has a secondary function as a synchronization input. 71 cvdd18 1 .8 v clock supply. supplies clock receivers, clock distribution, and pll circuitry. 72 cvdd18 1.8 v clock supply. supplies clock receivers, clock distribution, and pll circuitry. epad the exposed pad (epad) must be soldered to the ground plane (avss). t he epad provides an electrical, thermal, and mechanical connection to the board.
data sheet AD9121 rev. b | page 11 of 61 typical performance characteristics 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 50 100 150 200 250 300 350 400 450 harmonics (dbc) f out (mhz) f data = 250msps, second harmonic f data = 250msps, third harmonic f data = 400msps, second harmonic f data = 400msps, third harmonic 09988-101 figure 4. harmonics vs. f out over f data , 2 interpolation, digital scale = 0 dbfs, i fs = 20 ma 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 50 100 150 200 250 300 350 400 450 harmonics (dbc) f out (mhz) f data = 100msps, second harmonic f data = 100msps, third harmonic f data = 200msps, second harmonic f data = 200msps, third harmonic 09988-102 figure 5. harmonics vs. f out over f data , 4 interpolation, digital scale = 0 dbfs, i fs = 20 ma 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 100 200 300 400 500 600 700 harmonics (dbc) f out (mhz) f data = 100msps, second harmonic f data = 100msps, third harmonic f data = 150msps, second harmonic f data = 150msps, third harmonic 09988-103 figure 6. harmonics vs. f out over f data , 8 interpolation, digital scale = 0 dbfs, i fs = 20 ma 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 50 100 150 200 250 300 350 400 450 second harmonic (dbc) f out (mhz) 0dbfs ?6dbfs ?12dbfs ?18dbfs 09988-104 figure 7. second harmonic vs. f out over digital scale, 2 interpolation, f data = 400 msps, i fs = 20 ma 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 50 100 150 200 250 300 350 400 450 third harmonic (dbc) f out (mhz) 0dbfs ?6dbfs ?12dbfs ?18dbfs 09988-105 figure 8. third harmonic vs. f out over digital scale, 2 interpolation, f data = 400 msps, i fs = 20 ma 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 50 100 150 200 250 300 350 400 450 harmonics (dbc) f out (mhz) i fs = 10ma, second harmonic i fs = 20ma, second harmonic i fs = 30ma, second harmonic i fs = 10ma, third harmonic i fs = 20ma, third harmonic i fs = 30ma, third harmonic 09988-106 figure 9. harmonics vs. f out over i fs , 2 interpolation, f data = 400 msps, digital scale = 0 dbfs
AD9121 data sheet rev. b | page 12 of 60 ?69 ?70 ?71 ?72 ?73 ?74 ?75 ?77 ?78 ?79 0 50 100 150 200 250 300 350 400 450 highest digi t al spur (dbc) f out (mhz) ?76 f dat a = 250msps f dat a = 400msps 09988-107 figure 10 . highest digital spur vs. f out over f data , 2 interpolation, digital scale = 0 dbfs, i fs = 20 ma ?60 ?65 ?70 ?75 ?80 ?85 0 50 100 150 200 250 300 350 400 450 highest digi t a l spur (dbc) f out (mhz) f d at a = 100msps f d at a = 200msps 09988-108 figure 11 . highest digital spur vs. f out over f data , 4 interpolation, digital scale = 0 dbfs, i fs = 20 ma ?60 ?95 ?90 ?85 ?80 ?75 ?70 ?65 0 100 200 300 400 500 600 700 highest digi t a l spur (dbc) f out (mhz) f d at a = 100msps f d at a = 150msps 09988-109 figure 12 . highest digital spur vs. f out over f data , 8 interpolation, digital scale = 0 dbfs, i fs = 20 ma st art 1.0mhz #res bw 10khz vbw 10khz st op 500.0mhz swee p 6.017s (601 pts) 2 interpol a tion, single- t one spectrum, f dat a = 250msps, f out = 101mhz 09988- 1 10 figure 13 . single - tone spectrum , 2 interpolation , f data = 250 msps, f out = 101 mhz s t art 1.0mhz #res bw 10khz vbw 10khz s t o p 800.0mhz swee p 9.634s (601 pts) 4 interpol a tion, single- t one spectrum, f d at a = 200msps, f out = 151mhz 09988- 11 1 figure 14 . single - tone spectrum , 4 interpolation , f data = 200 msps, f out = 151 mhz s t art 1.0mhz #res bw 10khz vbw 10khz s t o p 800.0mhz swee p 9.634s (601 pts) 8 interpol a tion, single- t one spectrum, f d at a = 100msps, f out = 131mhz 09988- 1 12 figure 15 . single - tone spectrum , 8 interpolation , f data = 100 msps, f out = 131 mhz
data sheet AD9121 rev. b | page 13 of 60 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 100 150 200 250 300 350 400 450 imd (dbc) f out (mhz) f d at a = 250msps f d at a = 400msps 09988- 1 13 figure 16 . imd vs. f out over f data , 2 interpolation, digital scale = 0 dbfs, i fs = 20 ma 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 100 150 200 250 300 350 400 450 imd (dbc) f out (mhz) f d at a = 100msps f d at a = 200msps 09988- 1 14 figure 17 . imd vs. f out over f data , 4 interpolation, digital scale = 0 dbfs, i fs = 20 ma 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 100 150 200 250 300 350 400 450 imd (dbc) f out (mhz) f d at a = 100msps 09988- 1 15 figure 18 . imd vs. f out , 8 interpolation, f data = 100 msps, digital scale = 0 dbfs, i fs = 20 ma 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 100 150 200 250 300 350 400 450 imd (dbc) f out (mhz) ?6dbfs 0dbfs ?12dbfs ?18dbfs 09988- 1 16 figure 19 . im d vs. f out over digital scale, 2 interpolation, f data = 400 msps, i fs = 20 ma ?50 ?85 ?80 ?75 ?70 ?65 ?60 ?55 0 50 100 150 200 250 300 350 400 450 imd (dbc) f out (mhz) i fs = 20m a i fs = 30m a i fs = 10m a 09988- 1 17 figure 20 . imd vs. f out over i fs , 2 interpolation, f data = 400 msps, digital scale = 0 dbfs ?40 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 0 50 100 150 200 250 300 350 400 450 imd (dbc) f out (mhz) pl l off pl l on 09988- 1 18 figure 21 . imd vs. f out , 4 interpolation, f data = 200 msps, digital scale = 0 dbfs, i fs = 20 ma , pll on and pll off
AD9121 data sheet rev. b | page 14 of 60 ?152 ?156 ?154 ?158 ?160 ?162 ?164 ?166 0 50 100 150 200 250 300 350 400 450 nsd (dbm/hz) f out (mhz) 2, f d at a = 200msps 1, f d at a = 200msps 4, f d at a = 200msps 8, f d at a = 100msps 09988- 1 19 figure 22 . one - tone nsd vs. f out over interpolation , digital scale = 0 dbfs, i fs = 20 ma, pll off ?154 ?158 ?156 ?160 ?162 ?164 ?166 ?168 0 50 100 150 200 250 300 350 400 450 nsd (dbm/hz) f out (mhz) ?6dbfs 0dbfs ?12dbfs ?18dbfs 09988-120 figure 23 . one - tone nsd vs. f out over digital scale, 4 interpolation, f data = 200 msps, i fs = 20 ma, pll off ?158 ?159 ?160 ?161 ?162 ?163 ?164 ?165 ?166 0 50 100 150 200 250 300 350 400 450 nsd (dbm/hz) f out (mhz) 2, f d at a = 200msps 4, f d at a = 200msps 8, f d at a = 100msps 09988-121 figure 24 . one - tone nsd vs. f out over interpolation , digital scale = 0 dbfs, i fs = 20 ma, pll on ?161.0 ?165.5 ?165.0 ?164.5 ?164.0 ?163.5 ?163.0 ?162.5 ?162.0 ?161.5 0 50 100 150 200 250 300 350 400 450 nsd (dbm/hz) f out (mhz) 2, f dat a = 200msps 1, f dat a = 200msps 4, f dat a = 200msps 8, f dat a = 100msps 09988-122 figure 25 . eight - tone nsd vs. f out over interpolation , digital scale = 0 dbfs, i fs = 20 ma, pll off ?161.0 ?166.5 ?165.5 ?166.0 ?165.0 ?164.5 ?164.0 ?163.5 ?163.0 ?162.5 ?162.0 ?161.5 0 50 100 150 200 250 300 350 400 450 nsd (dbm/hz) f out (mhz) ?6dbfs 0dbfs ?12dbfs ?18dbfs 09988-123 figure 26 . eight - tone nsd vs. f out over digital scale, 4 interpolation, f data = 200 msps, i fs = 20 ma, pll off ?160 ?161 ?162 ?163 ?164 ?165 ?166 0 50 100 150 200 250 300 350 400 450 nsd (dbm/hz) f out (mhz) 2, f d at a = 200msps 4, f d at a = 200msps 8, f d at a = 100msps 09988-124 fig ure 27 . eight - tone nsd vs. f out over interpolation , digital scale = 0 dbfs, i fs = 20 ma, pll on
data sheet AD9121 rev. b | page 15 of 60 ?151 ?165 ?163 ?161 ?159 ?157 ?155 ?153 0 100 200 300 400 500 nsd (dbm/hz) f out (mhz) AD9121 nsd ad9122 nsd 09988-200 figure 28 . one - tone nsd vs. f out , f data = 400 msps, 2 interpolation , pll off (comparison of AD9121 vs . ad9122 ) ?77 ?84 ?83 ?82 ?81 ?80 ?79 ?78 0 50 100 150 200 250 aclr (dbc) f out (mhz) 0dbfs ?3dbfs ?6dbfs 09988-125 figure 29 . one - carrier w - cdma aclr vs. f out over digital scale , adjacent channel, pll off ?78 ?90 ?88 ?86 ?84 ?82 ?80 0 50 100 150 200 250 aclr (dbc) f out (mhz) 0dbfs ?3dbfs ?6dbfs 09988-126 figure 30 . one - carrier w - cdma aclr vs. f out over digit al scale , first alternate channel, pll off ?70 ?95 ?90 ?85 ?80 ?75 0 50 100 150 200 250 aclr (dbc) f out (mhz) 0dbfs ?3dbfs ?6dbfs 09988-127 figure 31 . one - carrier w - cdma aclr vs. f out over digital scale , second alternate channel, pll off ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 100 200 300 400 500 aclr (dbc) f out (mhz) interpol a tion f ac t or = 2, pl l off interpol a tion f ac t or = 4, pl l off interpol a tion f ac t or = 2, pl l on interpol a tion f ac t or = 4, pl l on 09988-128 figure 32 . one - carrier w - cdma aclr vs. f out over interp olation , adjacent channel, pll on and pll off ?70 ?72 ?74 ?76 ?78 ?80 ?82 ?84 ?86 ?88 ?90 0 100 200 300 400 500 aclr (dbc) f out (mhz) interpol a tion f ac t or = 2, pl l off interpol a tion f ac t or = 4, pl l off interpol a tion f ac t or = 2, pl l on interpol a tion f ac t or = 4, pl l on 09988-129 figure 33 . one - carrier w - cdma aclr vs. f out over interpolation , first alternate channel, pll on and pll off
AD9121 data sheet rev. b | page 16 of 60 ?70 ?95 ?90 ?85 ?80 ?75 0 100 200 300 400 500 aclr (dbc) f out (mhz) interpol a tion f ac t or = 2, pl l off interpol a tion f ac t or = 4, pl l off interpol a tion f ac t or = 2, pl l on interpol a tion f ac t or = 4, pl l on 09988-130 figure 34 . one - carrier w - cdma aclr vs. f ou t over interpolation , second alternate channel, pll on and pll off s t art 133.06mhz #res bw 30khz vbw 30khz s t o p 166.94mhz swee p 143.6ms (601 pts) rms resu l ts freq lower upper offset ref bw dbc dbm dbc dbm carrier power 5.00mhz 3.840mhz ?75.96 ?85.96 ?77.13 ?87.13 ?10.00dbm/ 10.00mhz 3.840mhz ?85.33 ?95.33 ?85.24 ?95.25 3.840mhz 15.00mhz 2.888mhz ?95.81 ?95.81 ?85.43 ?95.43 09988-131 figure 35 . one - carrier w - cdma aclr performance, if = ~150 mhz st art 125.88mhz #res bw 30khz vbw 30khz st op 174.42mhz swee p 206.9ms (601 pts) t ot al carrier power ? 1 1.19dbm/15.3600mhz rrc fi l ter: off fi l ter alph a 0.22 ref carrier power ?16.89dbm/3.84000mhz lower upper offset freq integ bw dbc dbm dbc dbm 1 ?16.92dbm 5.000mhz 3.840mhz ?65.88 ?82.76 ?67.52 ?84.40 2 ?16.89dbm 10.00mhz 3.840mhz ?68.17 ?85.05 ?69.91 ?86.79 3 ?17.43dbm 15.00mhz 3.840mhz ?70.42 ?87.31 ?71.40 ?88.28 4 ?17.64dbm 09988-132 figure 36 . four - carrier w - cdma aclr performance, if = ~150 mhz
data sheet AD9121 rev. b | page 17 of 60 t erminology integral nonlinearity (inl) inl is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation i n analog value, normalized to full scale, associated with a 1 lsb change in digital input code. offset error offset error is t he deviation of the output current from the ideal of 0 ma . for iout 1p , 0 ma output is expected when all inputs are set to 0. for i out 1n , 0 ma output is expected when all inputs are set to 1. gain error gain error is t he difference between the actual and ideal output span. the actual span is determined by the difference between the output when all inputs are set to 1 and the output w hen all inputs are set to 0. output compliance range the output compliance range is t he range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full - scale range (fs r) per degree celsius. for reference voltage drift, the drift is reported in ppm per degree celsius. power supply rejection (psr) psr is t he maximum change in the full - scale output as the supplies are varied from minimum to maximum specified voltages. sett ling time settling time is t he time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. spurious - free dynamic range (sfdr) sfdr is t he difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to nyquist frequency of the dac . typical ly, energy in this band is rejected by the interpolation filters. this specification, there - fore, defines how well the interp olation filters work and the effect of other parasitic coupling paths on the dac output. signal - to - noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency , excluding the first six harmonics and dc. the value for snr is expressed in decibels. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f d ata (interpolation rate), a digital filter can be constructed that has a sharp transition band near f d ata /2. images that typically appear around f dac (output data rate) can be greatly suppressed. adjacent channel leakage ratio (aclr) aclr is t he ratio , in decibels relative to the carrier ( dbc ) , between the measured power within a ch annel and that of its adjacent channel. complex image rejection in a traditional two - part upconversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the r eal part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected.
AD9121 data sheet rev. b | page 18 of 60 theory of operation the AD9121 combine s many features that make it a very attractive dac for wired and wireless communications systems. the dual digital signal path and dual dac structure allow an easy interface to common quadrature modulators when designing single side - band (ssb) transmitters. the speed and performance of the AD9121 allow wider bandwidths and more carriers to be syn - thesized than in previously available dacs. in addition, the AD9121 include s an innovative low power, 32 - bit , complex nco that greatly increases the ease of frequency placement. the AD9121 offers features that allow s implified synchroniza - tion with incoming data and between multiple devices. auxiliary dacs are also provided on chip. the auxiliary dacs can be used for output dc offset compensation (for lo compensation in ssb transmitters) and for gain matching (for imag e rejection optimiza - tion in ssb transmitters). s erial port operation the serial port is a flexible, synchronous serial communications port that allows easy interfacing to many industry - standard micro - controllers and microprocessors. the serial i/o is comp atible with most synchronous transfer formats, including both the motorola spi and intel? ssr protocols. the interface allows read/write access to all registers that configure the AD9121 . single - byte or multiple - byte transfer s are supported, as well as msb first or lsb first transfer formats. the serial port interface can be configured as a single - pin i/o (sdio) or as two unidi - rectional pi ns for input and output (sdio and sdo). 52 sclk 51 sdio 50 sdo 53 cs spi port 09988-010 figure 37 . serial port interface pins a communicat ion cycle with the AD9121 has two phases. phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight sclk rising edges. the instruction byte provides the serial port controller with information r eg arding the data transfer cycle phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is a read or write , along with the starting register address for the first byte of the data transfer. the first eig ht sclk rising edges of each communication cycle are used to write the in struction byte into the device. a logic high on the cs pin followed by a logic low resets the s erial port timing to the initial state of the instruction cycle. from this state, the next eight rising sclk edges represent the instruction bits of the current i/o operation . the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the device and the system controller . phase 2 of the communication cycle is a transfer of one or more data bytes . registers change immediately upon writing to the last bit of each transfer byte , e xcept for the frequency tuning word and nco phase offsets , which change only when the frequency tuning word (ftw) update bit (register 0x36, bit 0) is set. data format the instruction byte contains the information shown in table 9 . table 9. serial port instruction byte i7 (msb) i6 i5 i4 i3 i2 i1 i0 (lsb) r/ w a6 a5 a4 a3 a2 a1 a0 r/ w , bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. logic 1 indicates a read operation, and log ic 0 indicates a write operation. a6 to a0 , bit 6 to bit 0 of the instruction byte , determine the register that is accessed during the data transfer portion of the communication cycle. for multibyte transfers, a6 is the starting byte address. the remaining register addresses are generated by the device based on the lsb _first bit (register 0x00, bit 6). serial port pin desc riptions serial clock (sclk) the serial clock pin synchronizes data to and from the device and run s the internal state machines. the maxi mum frequency of sclk is 40 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip select ( cs ) an active low input starts and gates a communication cycle. it allows more tha n one device to be used on the same serial communications lines. when the cs pin is high, the sdo and sdio pins go to a high impedance state. during the communica - tion cycle, the cs pin should stay low. serial data i/o ( sdio) data is always written into the device on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by register 0x00, bit 7. the default is logic 0, configuring the sdio pin as unidirectional. s erial data ou tpu t (sdo) data is read from this pin for protocols that use separate lines for transmitting and receiving data. if the device operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state.
data sheet AD9121 rev. b | page 19 of 60 se rial port options the serial port can support both msb first and lsb first data formats. this functionality is controlled by the lsb_first bit (register 0x00, bit 6). the default is msb first ( lsb_first = 0). when lsb_first = 0 (msb first) , the instruction and data bit s must be written from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow from high address to low a ddress. in msb first mode, the serial port intern al byte address generator decre ments for each data byte of the multibyte communication cycle. when lsb_first = 1 (lsb first) , the instruction and data bit s must be written from lsb to msb. multibyte data tra nsfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte . subsequent data bytes should follow from low address to high address . in lsb first mode, the serial port internal byte address generator increments for each data byte of the multibyte communication cycle. if the msb first mode is active , t he serial port controller data address decrements from the data address written toward 0x00 for m ultibyte i/o operations . if the lsb first mode is active, the serial port controller data address increments from the data address written toward 0x7f for mult ibyte i/o operations . r/w a6 a5 a4 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle d at a transfer cycle cs sclk sdio sdo 09988-0 1 1 figure 38 . serial port interface timing, msb first sclk sdio sdo cs a0 a1 a2 a3 a4 a5 a6 d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle d at a transfer cycle r/w 09988-012 figure 39 . ser ia l port interface timing, lsb first sclk sdio cs instruction bit 6 instruction bit 7 t dcsb t ds t dh t pwh t pw l t sclk 09988-013 figure 40 . timing diagram for serial port register write sclk sdio, sdo cs d at a bit n ? 1 d at a bit n t dv 09988-014 figure 41 . timing diagram for serial port register read
AD9121 data sheet rev. b | page 20 of 60 device configuration register map and des cri ptions table 10 . device configuration register map addr (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0x00 comm sdio lsb_first reset 0x00 0x01 power control power down i dac power down q dac po wer down data receiver power down aux adc 0x10 0x03 data format binary data format q data first msb swap data bus width[1:0] 0x00 0x04 interrupt enable enable pll lock lost enable pll locked enable sync signal lost enable sync signal locked ena ble fifo warning 1 enable fifo warning 2 0x00 0x05 interrupt enable 0 0 0 enable aed compare pass enable aed compare fail enable sed compare fail 0 0 0x00 0x06 event flag pll lock lost pll locked sync signal lost sync signal locked fifo warning 1 fifo warning 2 n/a 0x07 event flag aed compare pass aed compare fail sed compare fail n/a 0x08 clock receiver control dacclk duty correction refclk duty correction dacclk cross - correction refclk cross - correction 1 1 1 1 0x3f 0x0a pll control pll enab le pll manual enable manual vco band[5:0] 0x40 0x0c pll control pll loop bandwidth[1:0] pll charge pump current[4:0] 0xd1 0x0d pll control n2[1:0] pll cross - control enable n0[1:0] n1[1:0] 0xd9 0x0e pll status pll locked vco control voltage[3:0] n/ a 0x0f pll status vco band readback[5:0] n/a 0x10 sync control sync enable data/fifo rate toggle rising edge sync sync averaging[2:0] 0x48 0x11 sync control sync phase request[5:0] 0x00 0x12 sync status sync lost sync locked n/a 0x13 sync status sync phase readback[7:0] (6.2 format) n/a 0x15 data receiver status lvds frame level high lvds frame level low lvds dci level high lvds dci level low lvds data level high lvds data level low n/a 0x16 dci delay dci delay[1:0] 0x00 0x17 fif o control fifo phase offset[2:0] 0x04 0x18 fifo status fifo warning 1 fifo warning 2 fifo soft align ack fifo soft align request n/a 0x19 fifo status fifo level[7:0] n/a 0x1b datapath control bypass premod bypass sinc ?1 bypass nco nco gain bypass phase comp and dc offset select sideband send i data to q data 0xe4
data sheet AD9121 rev. b | page 21 of 60 addr (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0x1c hb1 control hb1[1:0] bypass hb1 0x00 0x1d hb2 control hb2[5:0] bypass hb2 0x00 0x1e hb3 control hb3[5:0] bypass hb3 0x00 0x1f chip id chip id[7:0] 0x08 0x30 ftw lsb ftw[7:0] 0x00 0x31 ftw ftw[15:8] 0x00 0x32 ftw ftw[23:16] 0x00 0x33 ftw msb ftw[31:24] 0x0 0 0x34 nco phase offset lsb nco phase offset[7:0] 0x00 0x35 nco phase offset msb nco phase offset[15:8] 0x00 0x36 nco ftw update f rame ftw ack frame ftw request update ftw ack update ftw request 0x00 0x38 i phase adj lsb i phase adj[7:0] 0x00 0x39 i phase adj msb i phase adj[9:8] 0x00 0x3a q phase adj lsb q phase adj[7:0] 0x00 0x3b q phase adj msb q phase adj[9:8] 0 x00 0x3c i dac offset lsb i dac offset[7:0] 0x00 0x3d i dac offset msb i dac offset[15:8] 0x00 0x3e q dac offset lsb q dac offset[7:0] 0x00 0x3f q dac offset msb q dac offset[15:8] 0x00 0x40 i dac fs adjust i dac fs adj[7:0] 0xf9 0x41 i dac control i dac sleep i dac fs adj[9:8] 0x01 0x42 i aux dac data i aux dac[7:0] 0x00 0x43 i aux dac control i aux dac sign i aux dac current direction i aux dac sleep i aux dac[9:8] 0x00 0x44 q dac fs adjust q dac fs adj[7:0] 0xf9 0x45 q dac control q dac sleep q dac fs adj[9:8] 0x01 0x46 q aux dac d ata q aux dac[7:0] 0x00 0x47 q aux dac control q aux dac sign q aux dac current direction q aux dac sleep q aux dac[9:8] 0x00 0x48 die temp range control fs current[2:0] ref erence current[2:0] capac itor value 0x02 0x49 die temp lsb die temp[7:0] n/a 0x4a die temp msb die temp[15:8] n/a 0x67 sed control sed compare enable sample error detected autoc l ear enable compare fail compare pass 0x00 0x68 com p are i 0 lsbs compare value i0[7:0] 0xb6 0x69 compare i0 msbs compare value i0[15:8] 0x7a 0x6a compare q0 lsbs compare value q0[7:0] 0x45 0x6b compare q0 msbs compare value q0[15:8] 0xea
AD9121 data sheet rev. b | page 22 of 60 addr (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0x6c com p are i 1 lsbs compare value i1[7:0] 0x16 0x6d compare i1 msbs compare value i1[15:8] 0x1a 0x6e comp are q1 lsbs compare value q1[7:0] 0xc6 0x6f compare q1 msbs compare value q1[15:8] 0xaa 0x70 sed i lsbs errors detected i_bits[7:0] 0x00 0x71 sed i msbs errors detected i_bits[15:8] 0x00 0x72 sed q lsbs errors detected q_bits[7:0] 0x00 0x73 sed q ms bs errors detected q_bits[15:8] 0x00 0x7f revision 0 0 revision[3:0] 0 0 n/a table 11. device configuration register descriptions reg ister name addr ess (hex) bit s name description default comm 0x 0 0 7 sdio sdio pin o peration. 0 0 = sdio operates as an input only. 1 = sdio operates as a bidirectional input/output . 6 lsb_first serial port communication , lsb or msb first. 0 0 = msb first . 1 = lsb first . 5 reset the device is placed in reset when this bit is written high and remains in reset until the bit is written low. 0 power control 0x01 7 power down i dac 1 = power down i dac. 0 6 power down q dac 1 = power down q dac. 0 5 power d own d ata r eceiver 1 = p ower down the input data receiver . 0 4 power d own auxiliary adc 1 = p ower down the auxiliary adc for temperature sensor. 1 data format 0x03 7 binary data format 0 = input data is in twos complement format. 0 1 = input data is in binary format. 6 q d ata f irst indicates i/q data pairin g on data input. 0 0 = i d ata sent to data receiver first . 1 = q d ata sent to data receiver first . 5 msb swap swaps the bit order of the data input port. 0 0 = order of the data bits corresponds to the pin descriptions . 1 = bit de signations are swapped; most significant bits become the least significant bits . [1:0] data b us w idth [1:0] data receiver interface mode . see the lvds input data ports section for information about the operation of the different interface modes. 0 0 00 = w ord m ode ; 14 - bit interface bus width . 01 = b yte m ode ; 7 - bit interface bus width . 10 = invalid . 11 = i nvalid . interrupt enable 0x 0 4 7 enable pll lock lost 1 = e nable interrupt for pll lock lost . 0 6 enable pll l ocked 1 = e nable interrupt for pll l ocked. 0 5 enable sync signal lost 1 = e nable interrupt for sync signal lost . 0 4 enable sync signal locked 1 = e nable interrupt for sync signal locked . 0 1 enable fifo warning 1 1 = e n able interrupt for fifo warning 1. 0 0 enable fifo warning 2 1 = enable interrupt for fifo warning 2. 0
data sheet AD9121 rev. b | page 23 of 60 reg ister name addr ess (hex) bit s name description default interrupt enable 0x 0 5 [ 7 :5] set to 0 set th ese bit s to 0 . 0 00 4 enable aed compa re pass 1 = enable interrupt for aed comparison pass. 0 3 enab le aed compare fail 1 = enable interrupt for aed comparison fail. 0 2 enable sed compare fail 1 = enable interrupt for sed comparison fail. 0 [ 1 :0] set to 0 set th e s e bit s to 0 . 0 0 event flag 0x06 7 pll lock lost 1 = indicates that the pll, which h ad been previously locked, has unlocked from the reference signal. this is a latched signal. n/a 6 pll locked 1 = indicates that the pll has locked to the reference clock input. n/a 5 sync signal lost 1 = indicates that the sync logic, which had be en previously locked, has lost alignment. this is a latched signal. n/a 4 sync signal locked 1 = indicates that the sync logic has achieved sync alignment. this is indicated when no phase changes were requested for at least a few full averaging cycles. n/a 1 fifo warning 1 1 = indicates that the difference between the fifo read and write pointers is 1. n/a 0 fifo warning 2 1 = indicates that the difference between the fifo read and write pointers is 2. n/a note that all event flags are clea red by writing the respective bit high. 0x07 4 aed compare pass 1 = indicates that the sed logic detected a valid input data pattern compared against the preprogrammed expected values. this is a latched signal. n/a 3 aed compare fail 1 = indicates th at the sed logic detected an invalid input data pattern compared against the preprogrammed expected values. this latched signal is automatically clear ed when eight valid i/q data pairs are received. n/a 2 sed compare fail 1 = indicates that the sed logi c detected an invalid input data pattern compared against the preprogrammed expected values. this is a latched signal. n/a note that all event flags are cleared by writing the respective bit high. clock receiver control 0x 0 8 7 dacclk duty correction 1 = enable duty cycle correction on the dacclk input. 0 6 refclk duty correction 1 = enable duty cycle correction on the refclk input. 0 5 dacclk cross - correction 1 = enable differential crossing correction on the dac clk input. 1 4 refclk cross - co rrection 1 = enable differential crossing correction on the refclk input. 1 pll control 0x 0a 7 pll enable 1 = enable the pll clock multiplier. the refclk input is used as the pll reference clock signal. 0 6 pll manual enable 1 = enable manual selection of the vco band. the correct vco band must be determined by the user and written to bits[5:0]. 1 [5:0] manual vco b and [5:0] selects the vco band to be used. 0 000 0 0 0x 0c [ 7:6 ] pll loop bandwidth[1:0] selects the pll loop filter bandwidth. 11 00 = w id est bandwidth. 11 = narrow est bandwidth. [4:0] pll charge pump current[4:0] sets the nominal pll charge pump current. 10001 00000 = lowest current setting. 11111 = highest current setting.
AD9121 data sheet rev. b | page 24 of 60 reg ister name addr ess (hex) bit s name description default pll control 0 x0 d [ 7:6 ] n 2[1:0] pll control clock divider. this divider determines the ratio of the ref clk frequency to the pll controller clock frequency . f pc_clk must always be less than 75 mhz. 11 00 = f ref clk /f pc_clk = 2. 01 = f ref clk /f pc_clk = 4. 10 = f ref clk /f pc_clk = 8. 11 = f ref clk /f pc_clk = 16. 4 pll cross - control enable 1 = e nable pll cross - point controller . 1 [ 3:2 ] n0[1:0] pll vco divider. this divider determines the ratio of the vco frequency to the dacclk frequency . 10 00 = f vco /f dacc lk = 1. 01 = f vco /f dacclk = 2. 10 = f vco /f dacclk = 4. 11 = f vco /f dacclk = 4. [1:0] n1[1:0] pll l oop divider. this divider determines the ratio of the dacclk frequency to the refclk frequency . 01 00 = f dacclk /f refclk = 2. 01 = f dacclk /f refclk = 4. 10 = f dacclk /f refclk = 8. 11 = f dacclk /f refclk = 16. pll status 0x0e 7 pll lock ed 1 = t he pll - generated clock is tracking the refclk input signal. n/a [3:0] vco control voltage[3:0] vco control voltage readback. see table 24. n/a 0x0f [5:0] vco band readback[5:0] indicates the vco band currently selected. n/a sync control 0x 10 7 sync enable 1 = enable the synchronization logic. 0 6 data/fifo rate toggle 0 = operate the synchronization at the fifo reset rate. 1 1 = operate the synchronization at the data rate. 3 rising edge sync 0 = sync is initiated on the falling edge of the sync input. 1 1 = sync is initiated on the rising edge of the sync input. [ 2:0 ] sync averaging[2:0] s ets the number of input samples that are averaged in determining the sync phase. 0 00 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128. 0x 11 [5:0] sync phase request[5:0] this register sets the requested clock phase offset after sync. the offset unit is in dacclk cycles. this register enables repositioning of the dac output with respect to the sync input. the offset can also be used to skew the dac outputs bet ween the synchronized dacs. 0 00000 000000 = 0 dacclk cycles. 000001 = 1 dacclk cycle. 111111 = 63 dacclk cycles.
data sheet AD9121 rev. b | page 25 of 60 reg ister name addr ess (hex) bit s name description default sync status 0x12 7 sync lost 1 = synchronization was attained but has been lost. n/a 6 sync locked 1 = synchroniz ation has been attained. n/a 0x13 [7:0] sync phase readback[7:0] indicates the averaged sync phase offset (6.2 format). if this value differs from the sync phase request[5:0] value in register 0x11, a sync timing error has occurred. for more informatio n, see the sync status bits section. n/a 00000000 = 0.0. 00000001 = 0.25. 11111110 = 63.50. 11111111 = 63.75. data receiver status 0x15 5 lvds frame level high one or both lvds frame input signals have exceeded 1.7 v. n/a 4 lvds frame level low one or both lvds frame input signals have crossed below 0.7 v. n/a 3 lvds dci level high one or both lvds dci input signals have exceeded 1.7 v. n/a 2 lvds dci level low one or both lvds dci input si gnals have crossed below 0.7 v. n/a 1 lvds data level high one or more lvds dx input signals have exceeded 1.7 v. n/a 0 lvds data level low one or more lvds dx input signals have crossed below 0.7 v. n/a dci delay 0x 16 [1:0] dci delay[1:0] this op ti on is available for the r evision 2 silicon only . the dci d elay bits control the delay applied to the dci signal. the dci delay affects the sampling interval of the dci with respect to the dx inputs. see table 13. 00 = 350 p s delay of dci signal. 01 = 590 ps delay of dci signal. 10 = 800 ps delay of dci signal. 11 = 925 ps delay of dci signal. 0 0 fifo control 0x 17 [ 2:0 ] fifo phase offset[2:0] fifo write pointer phase offset following fifo reset. this is the difference between t he read pointer and the write pointer values upon fifo reset. the optimal value is nominally 4 (100) . 100 000 = 0. 001 = 1. 111 = 7. fifo status 0x18 7 fifo warning 1 1 = fifo read and write pointers are within 1. n/a 6 fifo warning 2 1 = fifo read and write pointers are within 2. n/a 2 fifo soft align acknowledge 1 = fifo read and write pointers are aligned after a serial port initiated fifo reset. n/a 1 fifo soft align request 1 = r equest fifo read and write pointer a lignment via the serial port. 0 0x19 [7:0] fifo level[7:0] thermometer encoded measure of the fifo level. n/a
AD9121 data sheet rev. b | page 26 of 60 reg ister name addr ess (hex) bit s name description default datapath control 0x 1b 7 bypass p remod 1 = bypass the f s /2 premodulator. 1 6 bypass s inc ? 1 1 = bypass the inverse sinc filter. 1 5 bypass nco 1 = bypass the nc o. 1 3 nco gain 0 = n o gain scaling is applied to the nco input to the internal digital modulator ( default) . 0 1 = gain scaling of 0.5 is applied to the nco input to the inte rnal digital modulator. gain scaling can eliminate satu - ration of the modulator output for some combinations of data inputs and nco signals. 2 bypass phase compensation and dc offset 1 = bypass phase compensation and dc offset . 1 1 select sideband 0 = the modulator outputs the high - side image. 0 1 = the modulator outputs the low - side image. the image is spectrally inverted compared to the input data. 0 send i data to q data 1 = ignore q data from the interface and disable the clocks to the q datapath. send i data to both the i and q dacs. 0 hb1 control 0x1c [2:1] hb1[1:0] modulation mode for i side half - band filter 1. 0 0 00 = input signal not modulated ; filter pass band is from ?0.4 to +0.4 of f in1 . 01 = input signal not modulate d ; filter pass band is from 0.1 to 0.9 of f in1 . 10 = input signal modulated by f in1 ; filter pass band is from 0.6 to 1.4 of f in1 . 11 = input signal modulated by f in1 ; filter pass band is from 1.1 to 1.9 of f in1 . 0 bypass hb1 1 = bypas s the first - stage interpolation filter. 0 hb2 control 0x 1d [ 6: 1 ] hb2[5 :0] modulation mode for i s ide half - band filter 2. 0 00000 000 000 = input signal not modu lated ; filter pass band is from ?0.25 to +0.25 of f in2 . 001001 = input signal not modu lated ; filter pass band is from 0.0 to 0.5 of f in2 . 010010 = input signal not modu lated ; filter pass band is from 0.25 to 0.75 of f in2 . 011 011 = input signal not modul ated ; filter pa ss band is from 0.5 to 1.0 of f in2 . 100100 = input signal modulated by f in2 ; filter pass band is from 0.75 to 1.25 of f in2 . 101 101 = input signal modulated by f in2 ; filter pass band is from 1.0 to 1.5 of f in2 . 110 110 = input signal mod ulated by f in2 ; filter pass band is from 1.25 to 1.75 of f in2 . 111 111 = input signal modulated by f in2 ; filter pass band is from 1.5 to 2.0 of f in2 . 0 bypass hb2 1 = bypass the second - stage interpolation filter. 0
data sheet AD9121 rev. b | page 27 of 60 reg ister name addr ess (hex) bit s name description default hb3 control 0x1e [6:1] hb3[5: 0] modulation mode for i side half - band filter 3. 0 00000 000000 = input signal not modu lated ; filter pass band is from ?0.2 to +0.2 of f in3 . 001 001 = input signal not modul ated ; filter pass band is from 0.05 to 0.45 of f in3 . 010010 = inpu t signal not modul ated ; filter pass band is from 0.3 to 0.7 of f in3 . 011011 = input signal not modulated ; filter pass band is from 0.55 to 0.95 of f in3 . 100 100 = input signal modulated by f in3 ; filter pass band is from 0.8 to 1.2 of f in3 . 101101 = input signal modulated by f in3 ; filter pass band is from 1.05 to 1.45 of f in3 . 110 110 = input signal modulated by f in3 ; filter pass band is from 1.3 to 1.7 of f in3 . 111 111 = input signal modulated by f in3 ; filter pass band is fr om 1.55 to 1.95 of f in3 . 0 bypass hb3 1 = bypass th e th ird - stage interpolation filter. 0 chip id 0x 1f [7:0] chip id[7:0] this register identifies the device as an AD9121 . 00001000 ftw lsb 0x 30 [7:0] ftw[7:0] see register 0x33. 0 0000000 ftw 0x 31 [7:0 ] ftw[15:8] see register 0x33. 00000000 ftw 0x 32 [7:0] ftw[23:16] see register 0x33. 00000000 ftw msb 0x 33 [7:0] ftw[31:24] ftw[31:0] is the 32 - bit frequency tuning word that deter - mines the frequency of the complex carrier generated by the on - c hi p nc o. the frequency is not updated when the ftw registers are written. the values are only updated when bit 0 of register 0x36 transitions from 0 to 1. 00000000 nco phase offset lsb 0x 34 [7:0] nco phase offset[7:0] see register 0x35. 00000000 nco phase offset msb 0x 35 [7:0] nco phase offset[15:8] the nco sets the phase of the complex carrier signal when the nco is reset. the phase offset spans from 0 to 360. each bit represents an offset of 0.0055. this v alue is in twos complement format. 00000000 nco ftw update 0x 36 5 frame ftw acknowledge 1 = the nco has been reset due to an extended frame pulse signal. 0 4 frame ftw request 0 = the nco is reset on the first extended frame pulse after this bit is set to 1. 0 1 update ftw acknowledge 1 = the ftw has been updated. 0 0 update ftw request t he ftw is updated on the 0 - to - 1 transition of this bit. 0 i phase adj lsb 0x 38 [7:0] i phase adj[7:0] see register 0x39. 00000000 i phase adj msb 0x 39 [1:0] i phase adj[9:8] i phase adj[9:0] is used to insert a ph ase offset between the i and q datapaths. this offset can be used to correct for phase imbalance in a quadrature modulator. see the quadrature phase correction section for more information . 0 0 q phase adj lsb 0x 3a [7:0] q phase adj[7:0] see register 0x3b. 00000000 q phase adj msb 0x 3b [1:0] q phase adj[9:8] q phase adj[ 9 :0] is used to insert a phase offset between the i and q datapaths. this offset can be used to correct for phase imbalance in a quadrature mod ulator. see the quadrature phase correction section for more information . 0 0 i dac offset lsb 0x 3c [7:0] i dac offset[7:0] see register 0x3d. 00000000 i dac offset msb 0x 3d [7:0] i dac offset[15:8] i dac offset[1 5:0] is a value that is added directly to the samples written to the i dac. 00000000
AD9121 data sheet rev. b | page 28 of 60 reg ister name addr ess (hex) bit s name description default q dac offset lsb 0x 3e [7:0] q dac offset[7:0] see register 0x3f. 00000000 q dac offset msb 0x 3f [7:0] q dac offset[15:8] q dac offset[15:0] is a value that is added dire ctly to the samples written to the q dac. 00000000 i dac fs adjust 0x 40 [7:0] i dac fs adj[7:0] see register 0x41, bits[1:0]. 11111001 i dac control 0x 41 7 i dac sleep 1 = puts the i dac into sleep mode (fast wake - up mode). 0 [1:0] i dac fs a dj [9:8] i dac fs adj[9:0] sets the full - scale current of the i dac. the full - scale current can be adjusted from 8.64 ma to 31.6 8 ma in step sizes of approximately 22.5 a. 0 1 0x000 = 8.64 ma. 0x200 = 20.16 ma. 0x3ff = 31.68 ma. i aux dac data 0x 42 [7:0] i aux dac [7:0] see register 0x43, bits[1:0]. 00000000 i aux dac control 0x 43 7 i aux dac sign 0 = the i auxiliary dac sign is positive, and the current is directed to the iout1p pin (pin 67). 0 1 = the i auxiliary dac sign is negative, and the current is directed to the iout 1 n pin (pin 66). 6 i aux dac current direction 0 = the i auxiliary dac sources current. 0 1 = the i auxiliary dac sinks current. 5 i aux dac sleep 1 = puts the i auxiliary dac into sleep mod e. 0 [1:0] i a ux dac[9:8] i aux dac[9:0] sets the magnitude of the auxiliary dac current. the range is 0 ma to 2 ma, and the step size is 2 a. 0 0 0x000 = 0.000 ma. 0x001 = 0.002 ma. 0x3ff = 2.046 ma. q dac fs adjust 0x 44 [7: 0] q dac fs adj[7:0] see register 0x45, bits[1:0]. 11111001 q dac control 0x 45 7 q dac sleep 1 = puts the q dac into sleep mode (fast wake - up mode). 0 [1:0] q dac fs adj [9:8] q dac fs adj[9:0] sets the full - scale current of the q dac. the full - scale cu rrent can be adjusted from 8.64 ma to 31.6 8 ma in step sizes of approximately 22.5 a. 0 1 0x000 = 8.64 ma. 0x200 = 20.16 ma. 0x3ff = 31.68 ma. q aux dac data 0x 46 [7:0] q aux dac [7:0] see register 0x47, bits[1:0]. 0 0000000
data sheet AD9121 rev. b | page 29 of 60 reg ister name addr ess (hex) bit s name description default q aux dac control 0x 47 7 q aux dac sign 0 = the q auxiliary dac sign is positive, and the current is directed to the iout2p pin (pin 58). 0 1 = the q auxiliary dac sign is negative, and the current is directed to the iout2n pin (pin 59). 6 q a ux dac current direction 0 = the q auxiliary dac sources current. 0 1 = the q auxiliary dac sinks current. 5 q aux dac s leep 1 = puts the q auxiliary dac into sleep mode. 0 [1:0] q a ux dac[9:8] q aux dac[9:0] sets the magnitude of the auxiliary dac current. the range is 0 ma to 2 ma, and the step size is 2 a. 0 0 0x000 = 0.000 ma. 0x001 = 0.002 ma. 0x3ff = 2.046 ma. die temp range control 0x48 [6:4] fs current[2:0] auxiliary adc full - scale current. 000 000 = lowes t current. 111 = high est current. [ 3:1 ] reference current[2:0] auxiliary adc reference current. 00 1 000 = lowest current. 111 = highest current. 0 capacitor value auxiliary adc internal capacitor value. 0 0 = 5 p f. 1 = 10 pf. die temp lsb 0x49 [7:0] die temp[7:0] see register 0x4a. n/a die temp msb 0x4a [7:0] die temp[15:8] die temp[15:0] indicates the approximate die temperature. for more information, s ee the te mperature sensor section. n/a sed control 0x 67 7 sed compare enable 1 = enable the sed circuitry. none of the flags in this register or the values in register 0x70 through register 0x73 are significant if the sed is not enabled. 0 5 sample error detec ted 1 = indicates that an error wa s detected. the bit remains set until cleared. any write to this register clears this bit to 0. 0 3 auto clear enable 1 = enable auto clear mode. this activates bit 1 and bit 0 of this register and causes register 0x70 t h rough register 0x73 to be auto cleared when eight consecutive sample data sets are received error free. 0 1 compare fail 1 = indicates that an error w as detected. this bi t remains set until it is auto cleared by the recept ion of eight consecutive error - fr ee comparisons or is cleared by a write to this register. 0 0 compare pass 1 = indicates that the last sample comparison was error free. 0 compare i0 lsb s 0x 68 [7:0] compare value i0[7:0] see register 0x69. 10110110 compare i0 msb s 0x 69 [7:0] compar e value i0[15:8] compare value i0[15:0] is the word that is compared with the i0 input sample captured at the input interface. 01111010 compare q0 lsb s 0x 6a [7:0] compare value q0[7:0] see register 0x6b. 01000101 compare q0 msbs 0x 6b [7:0] compare valu e q0[15:8] compare value q0[15:0] is the word that is compared with the q0 input sample captured at the input interface. 11101010 compare i1 lsb s 0x 6c [7:0] compare value i1[7:0] see register 0x6d. 00010110 compare i1 msb s 0x 6d [7:0] compare value i1[1 5:8] compare value i1[15:0] is the word that is compared with the i1 input sample captured at the input interface. 00011010
AD9121 data sheet rev. b | page 30 of 60 reg ister name addr ess (hex) bit s name description default compare q1 lsb s 0x 6e [7:0] compare value q1[7:0] see register 0x6f. 11000110 compare q1 msb s 0x 6f [7:0] compare value q1[15:8] compare value q1[15:0] is the word that is compared with the q1 input sample captured at the input interface. 10101010 sed i lsb s 0x 70 [7:0] errors detected i_bits[7:0] see register 0x71. 0 0000000 sed i msb s 0x 71 [7:0] errors detected i_bits[15:8] er rors detected i_bits[15:0] indicates which bits were received in error. 00000000 sed q lsb s 0x 72 [7:0] errors detected q_bits[7:0] see register 0x73. 00000000 sed q msb s 0x 73 [7:0] errors detected q_bits[15:8] errors detected q_bits[15:0] indicates w hich bits were received in error. 00000000 revision 0x 7f [ 5:2 ] revision[3:0] this value corresponds to the die revision number. 0011
data sheet AD9121 rev. b | page 31 of 60 lvds input data port s the AD9121 has one lvds data port that receives data for both the i and q transmit paths. the de vice can accept data in word and byte formats . in word mode , the data is sent over a 14- bit lvds data bus. in byte mode, the data is sent over an 8 - bit lvds data bu s in the format of msb[d13:d6] + lsb[d5:d0]. the 14 - bit word is split into a n 8 - bit msb port ion and a 6 - bit lsb portion. the lsb portion should be msb aligned with the 8 - bit lvds data bus. the pin assignment s of the bus in each mode are shown in table 12. table 12. data bit pair a s signments for data input modes mode msb to lsb word d1 3 , d1 2 , , d0 byte 1 d1 2 , d1 0 , d 8 , d 6 , d 5 , d 3 , d 1 , bytelsb 1 in byte mode , the unused pins can be left floating. the data is accompanied by a reference bit (dci) that is used to generate a double dat a rate (ddr) clock. in byte mode , a frame signal is required for controlling to which dac the data is sent . all of the interface signals are time aligned , so ther e is a maxi mum skew requirement on the bus . word interface mode in word mode, the dci signal i s a reference bit used to generat e the data sampling clock . the dci signal should be t ime align ed with the data . the i dac data should correspond to dci high , and the q dac data should correspond to dci low , as shown in figure 42. dci q 0 i 1 q 1 i 2 q 2 i 3 q 3 d at a[13:0] 09988-015 figure 42 . timing diagram for word mode byte interface mode in byte mode, the dci signal is a reference bit used to generat e the data sampling clock. the dci signal should be time aligned with the data . the most significant byte of the data should corre - spond to dci high , and the least significant byte of the data should correspond to dci low . the frame signal indicates to which dac the data is sent . when frame is high, data is sent to the i dac ; w hen frame is lo w, data is sent to the q dac . the complete timing diagram is shown in figure 43. interface timing the timing diagram for the digital interface port is shown in figure 44 . t he sampling point of the data bus nominally occurs 350 ps after each edge of the dci signal and has an uncertainty of 300 ps, as illustrated by the sampling interval shown in figure 44 . the data and frame signals must be valid through - out this sampling interval. the data and frame signals may change at any time between sampling intervals. dci dat a[13:0] frame q 0lsb i 1msb i 1lsb q 1msb q 1lsb i 2msb i 2lsb q 2msb q 2lsb 09988-016 figure 43 . timing diagram for byte mode
AD9121 data sheet rev. b | page 32 of 61 the setup (t s ) and hold (t h ) times, with respect to the edges, are shown in figure 44. the minimum setup and hold times are shown in table 13. dci data t data t data sampling interval sampling interval t s t s t h t h 09988-146 figure 44. timing diagram for input data port table 13. data to dci setup and hold times dci delay register 0x16, bits[1:0] minimum setup time, t s (ns) minimum hold time, t h (ns) sampling interval (ns) 00 ?0.05 0.65 0.6 01 ?0.23 0.95 0.72 10 ?0.38 1.22 0.84 11 ?0.47 1.38 0.91 the data interface timing can be verified by using the sample error detection (sed) circuitry. see the interface timing validation section for more information. recommended frame input bias circuitry because the frame signal can be used as a reference clock in the byte mode or as a trigger to reset the fifo, it is recommended that the frame input be tied to lvds logic low when it is not used (that is, when it is not driven by an asic or fpga). the external bias circuit shown in figure 45 is recommended for this purpose. 0 9988-145 100? 150 ? 51? ad9122 framep framen 5 6 dvdd18 (1.8v) figure 45. external bias circuit fifo operation the AD9121 contains a 2-channel, 14-bit wide, eight-word deep fifo designed to relax the timing relationship between the data arriving at the dac input ports and the internal dac data rate clock. the fifo acts as a buffer that absorbs timing variations between the data source and the dac, such as the clock-to-data variation of an fpga or asic, which significantly increases the timing budget of the interface. figure 46 shows the block diagram of the datapath through the fifo. the data is latched into the device, is formatted, and is then written into the fifo register determined by the fifo write pointer. the value of the write pointer is incremented every time a new word is loaded into the fifo. meanwhile, data is read from the fifo register determined by the read pointer and fed into the digital datapath. the value of the read pointer is incremented every time data is read into the datapath from the fifo. the fifo pointers are incremented at the data rate (dacclk rate divided by the interpolation ratio). valid data is transmitted through the fifo as long as the fifo does not overflow or become empty. an overflow or empty condition of the fifo occurs when the write pointer and read pointer point to the same fifo location. this simultaneous access of data leads to unreliable data transfer through the fifo and must be avoided. nominally, data is written to and read from the fifo at the same rate. this keeps the fifo depth constant. if data is written to the fifo faster than data is read out, the fifo depth increases. if data is read out of the fifo faster than data is written to it, the fifo depth decreases. for optimum timing margin, the fifo depth should be maintained near half full (a difference of 4 between the write pointer and read pointer values). the fifo depth represents the fifo pipeline delay and is part of the over- all latency of the AD9121.
data sheet AD9121 rev. b | page 33 of 60 iand q dacs 28 28 28 28 bits int dci dacclk data i and q data paths data format input latch reg 0 reg 1 reg 2 reg 3 reg 4 reg 5 reg 6 reg 7 reset logic frame sync fifo soft align request reg 0x18[1] data/fifo rate reg 0x10[6] fifo phase offset reg 0x17[2:0] read pointer reset write pointer reset read pointer write pointer 09988-018 figure 46. block diagram of fifo
AD9121 data sheet rev. b | page 34 of 60 resetting the fifo when the AD9121 is powered on, the fifo depth is unknown. to avoid a concurrent read and write to the same fifo address and to ensure a fixed pipeline delay, it is important to reset the fifo pointers to known states. th e fifo pointers can be initial- ized in two ways: via a write sequence to the serial port or by strobing the frame input. there are two types of fifo resets: a relative reset and an absolute reset. a relative reset enforces a defined fifo depth. an absolute reset enforces a particular write pointer value when the reset is initiated. a serial port initiated fifo reset is always a relative reset. a frame strobe initiated reset can be either a relative or an absolute reset. if the frame differential inputs are not used for fifo reset or for framing the word width, they must be tied to logic low. framep must be tied to dvss, and framen must be tied to dvdd18 to avoid accidental reset of the fifo due to noise. the operation of the frame initiated fifo reset depends on the synchronization mode chosen. ? when synchronization is disabled or when it is configured for data rate mode synchronization, the frame strobe initiates a relative fifo reset. the reference point of the relative reset is the position of the read pointer. ? when fifo mode synchronization is chosen, the frame strobe initiates an absolute fifo reset. for more information about the synchronization function, see the multichip synchronization section. a summary of the synchronization modes and the types of fifo reset used is provided in table 14. table 14. summary of fifo resets fifo reset signal synchronization mode disabled data rate fifo reset serial port relative relative relative frame relative relative absolute serial port initiated fifo reset a serial port initiated fifo reset can be issued in any synchro- nization mode and always results in a relative fifo reset. to initialize the fifo data level th rough the serial port, bit 1 of register 0x18 should be toggled from 0 to 1 and back. when the write to this register is complete, the fifo data level is initialized. when the initialization is triggered, the next time that the read pointer becomes 0, the write pointer is set to the value of the fifo start level variable (register 0x17, bits[2:0]) upon initialization. by default, this value is 4, but it can be programmed to a value from 0 to 7. it is recommended that a value of 5 (0x05) be pro- grammed in register 0x17. the recommended procedure for a serial port fifo data level initialization is as follows: 1. program register 0x17 to 0x05. 2. request fifo level reset by setting register 0x18, bit 1, to 1. 3. verify that the part acknowledges the request by ensuring that register 0x18, bit 2, is set to 1. 4. remove the request by setting register 0x18, bit 1, to 0. 5. verify that the part drops the acknowledge signal by ensuring that register 0x18, bit 2, is set to 0. 6. read back register 0x19 to verify that the pointer spacing is set to 3 (0x07) or 4 (0x0f). 7. if the readback of register 0x19 shows a pointer spacing of 2 (0x03), increment register 0x17 to a spacing of 0x06 and repeat step 2 through step 5. read back register 0x19 again to verify that the pointer spacing is now set to 3 (0x07). 8. if the readback of register 0x19 shows a pointer spacing of 5 (0x1f) after step 6, decrement register 0x17 to a spacing of 0x04 and repeat step 2 through step 5. read back register 0x19 again to verify that the pointer spacing is now set to 4 (0x0f). frame initiated rela tive fifo reset the primary function of the frame input is to indicate to which dac the input data is written. another function of the frame input is to initialize the fifo data level value. this is done by asserting the frame signal high for at least the time interval required to load complete data to the i and q dacs. this corresponds to one dci period in word mode and two dci periods in byte mode. to initiate a relative fifo reset with the frame signal, the device must be configured in data rate mode (register 0x10, bit 6 = 1). when frame is asserted in data rate mode, the write pointer is set to 4 by default (or to the fifo start level) the next time that the read pointer becomes 0 (see figure 47). 0 1 2 3 4 5 6 7 0 1 2 3 3 4 5 6 7 0 1 2 3 4 5 6 fifo write resets read pointe r frame write pointe r 09988-019 figure 47. frame input vs. write pointer value, data rate mode
data sheet AD9121 rev. b | page 35 of 60 frame initiated absolute fifo reset in fifo r ate synchronization mode, the write pointer of the fifo is reset in an absolute manner. the synchronization signal aligns the internal clocks on the part to a common reference clock so that the pipeline delay in the digital circuit stays the same during power cycles. the synchronization signal is sampled by the dac clock in the AD9121 . the edge of the dac c lock used to sample the synchronization signal is selected by bit 3 of r egis ter 0 x10. t he frame signal is used to reset the fifo write pointer. in the fifo rate synchronization mode, the fifo write pointer is reset immediately after the frame signal is asserted high for at least the time interval required to load complete data to the i and q dacs. t he fifo write pointer is reset to the value of the fifo phase offset[2:0] bits in r egister 0x17. fifo r ate synchro - nization is selected by set ting bit 6 of r egister 0x10 to 0. read pointer write pointer sync frame fifo read reset fifo write reset fifo phase offset[2:0] reg 0x17[2:0] = 101 0 1 3 2 1 0 7 6 5 4 3 2 3 2 1 0 7 6 5 6 6 5 4 7 09988-148 figure 48 . frame input vs. write pointe r value, fifo rate mode monitoring the fifo status the fifo i nitialization and stat us can be read from r egister 0x18 . this register provides information about the fifo status and whether the initialization wa s successful. the msb of r egister 0x18 is a fifo w arning flag that can optionally trigger a device irq . this flag indicates that the fifo is close to emptying (fifo level is 1) or overflowing (fifo l evel is 7) . in this case, data may soon be corrupted , and action should be taken . the fifo data level c an be read from r egister 0x19 at any time . the serial port reported fifo data level is denoted as a 7 - bit thermometer code (base 1 code) of the w rite counter state relative to the absolute r ead counter being at 0. the optimum fifo data lev el of 4 is therefore reported as a value of 00001111 in the status register . n ote that, depending on the timing relationship between the dci and the main dac clk, the fifo level value c an be off by a 1 count , that i s, the readback of register 0x19 can be 00011111 in the case of a +1 count and 00000111 in the case of a ? 1 count . therefore , it is important to keep the difference between the read and write pointers to a value of at least 2 .
AD9121 data sheet rev. b | page 36 of 60 digital data p ath the block diagram in figure 49 shows the functionality of the digital datapath. the digital processing includes a premodulation block, three half - band (hb) interpolation filters, a quadrature modulator with a fine resolution nco, phase and offset adjust - ment blocks , and an inverse sinc filter. premod phase and offset adjust hb1 hb2 hb3 sinc ?1 09988-020 figure 49 . block diagram of digital datapath the digital datapath accepts i and q data streams and processes them as a quadrature data stream. the signal processing blocks can be used when the input data stream is represented as complex data. the digital datap ath can also be used to process an input data stream representing two independent real data streams, but the functionality is somewhat restricted. the premodulation block and any of the nonshifted interpolation filter modes can be used for an input data st ream representing two independent real data streams . see the coarse modulation mixing sequences section for m ore information . premodulation the half - band interpolation filters have selectable pass bands that allow the center frequencies to be moved in increments of one - half their input data rate. the premodulation block provides a digital upconversion of the incoming waveform by one - half the incoming data rate, f data . th is can be used to frequency - shift base - band in put data to the center of the interpolation filte r pass band. interpolation filter s the transmit path contains three interpolation filters. each of the three interpolation filters provides a 2 increase in output data rate. the half - band (hb) filters can b e individually bypassed or cascaded to provide 1 , 2 , 4 , or 8 interpolation ratios . each half - band filter stage offers a different combination of bandwidths and operating modes. the bandwidth of the three half - band filters with respect to the data rate at the filter input is as follows: ? bandwidth of hb1 = 0.8 f in1 ? bandwidth of hb2 = 0.5 f in2 ? bandwidth of hb3 = 0.4 f in3 the usable bandwidth is defined as the frequency over which the filters have a pass - band ripple of less than 0.001 db and an imag e rejection of greater than + 85 db . as de sc rib ed in the half - band filter 1 (hb1) section , the image rejection usually sets the usable bandwidth of the filter , not the pass - band flatness. the half - band filters oper ate in several modes , providing programmable pass - band center frequencies as well as signal modulation . the hb1 filter has four modes of operation , and the hb2 and hb3 filters each have eight modes of operation . half - band filter 1 (hb1) hb1 has four modes of operation , as shown in figure 50 . the shape of the filter response is identical in each of the four modes . the four modes are distinguished by two factors : the filter center frequency and whether the input signa l is modulated by the filter. 0 ?20 ?40 ?60 ?80 ?100 0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 magnitude (db) frequenc y ( f in1 ) (hz) mode 0 mode 1 mode 3 mode 2 09988-021 figure 50 . hb1 filter modes as shown in figure 50 , the center frequency in each mode is offset by one - half the input data rate (f in1 ) of the filter . mode 0 a nd mode 1 do not modulate the input signal . mode 2 and mode 3 modulate the input signal by f in1 . when operating in m ode 0 and mode 2, the i and q paths operate independently and no mixing of the data between channels occurs . when oper - ating in m ode 1 and m ode 3, mixing of the data between the i and q paths occurs ; therefore, the data input in to the filter is assumed to be complex . table 15 summarizes the hb1 modes . table 15. hb1 filter modes mode f center f mod input data 0 dc none real or c omplex 1 f in /2 none complex 2 f in f in real or c omplex 3 3f in /2 f in complex
data sheet AD9121 rev. b | page 37 of 60 figure 51 shows the pass - band filter response for hb1 . i n most applications , the usab le bandwidth of the filter is limited by the image suppression provided by the stop - band rejection and not by the pass - band flatness. table 16 shows the pass - band flatness and stop - band rejection supported by th e h b1 filter at dif f erent bandwidths. 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.40 0.36 0.32 0.28 0.24 0.20 0.16 0.12 0.08 0.04 magnitude (db) frequenc y ( f in1 ) (hz) 09988-022 figure 51 . pass - band d etail of hb1 table 16. hb1 pass - band a nd stop - band performance by bandwidth bandwidth (% of f in1 ) pass - b and flatness (db) stop - b and rejection (db) 80 0.001 85 80.4 0.0012 80 81.2 0.0033 70 82 0.0076 60 83.6 0.0271 50 85.6 0.1096 40 half - band filter 2 (hb2) hb2 has eight modes of operation , as shown in figure 52 and figure 53 . the shape of the filter response is identical in each of the eight modes . the eight modes are distinguished by two factors : the filter center frequency and whether the input signal is modulated by the filter. 0 ?20 ?40 ?60 ?80 ?100 0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 magnitude (db) frequenc y ( f in2 ) (hz) mode 0 mode 2 mode 6 mode 4 09988-023 figure 52 . hb2, even filter modes 0 ?20 ?40 ?60 ?80 ?100 0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 magnitude (db) frequenc y ( f in2 ) (hz) mode 1 mode 3 mode 7 mode 5 09988-024 figure 53 . hb2, odd filter modes as shown in figure 52 and figure 53 , the center frequency in each mode is offs et by one - fourth the input data rate (f in2 ) of the filter . mode 0 through mode 3 do not modulate the input signal . mode 4 t hrough mode 7 modulate the input signal by f in2 . when operating in m ode 0 and mode 4, the i and q paths operate independently and no mixing of the data between chan - nels occurs . when operating in the other six modes, mixing of the data between the i and q paths occurs ; therefore, the data input to the filter is assumed to be complex .
AD9121 data sheet rev. b | page 38 of 60 table 17 s ummarizes the hb2 and hb3 modes. table 17. hb2 and hb3 filter modes mode f center f mod input data 0 dc none real or c omplex 1 f in /4 none complex 2 f in /2 none complex 3 3f in /4 none complex 4 f in f in real or c omplex 5 5f in /4 f in complex 6 3f in /2 f in complex 7 7 f in /4 f in complex figure 54 shows the pass - band filter response for hb2 . i n most applications , the usable bandwidth of the filter is limited by the image suppression provided by the stop - band rejection and not by the pass - band flatness. table 18 shows the pass - band flatness and stop - band rejection supported by th e hb2 filter at differ ent bandwidths. 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 0 0.32 0.28 0.24 0.20 0.16 0.12 0.08 0.04 magnitude (db) frequenc y ( f in2 ) (hz) 09988-025 figure 54 . pa ss- band d etail of hb2 table 18. hb2 pass - b and and stop - band performance by bandwidth bandwidth (% of f in2 ) pass - b and flatness (db) stop - b and rejection (db) 50 0.001 85 50.8 0.0012 80 52.8 0.0028 70 56 0.0089 60 60 0.0287 50 64.8 0.1877 40 half - band filter 3 (hb3) hb3 has eight modes of operation that function the same as hb2 . the primary difference between hb2 and hb3 is the filter bandwidths . figure 55 shows the pass - band filter re sponse for hb3. in most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop - band rejection and not by the pass - band flatness. table 19 shows the pass - band flatn ess and stop - band rejection supported by the hb3 filter at different bandwidths. 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.28 0.24 0.20 0.16 0.12 0.08 0.04 magnitude (db) frequenc y ( f in3 ) (hz) 09988-026 figure 55 . pass - b and d etail of hb3 table 19. hb3 pass - b and and stop - band performance by bandwidth bandwidth (% of f in3 ) pass - b and flatness (db) stop - b and rejection (db) 40 0.001 85 40.8 0.0014 80 42.4 0.002 70 45.6 0.0093 60 49.8 0.03 50 55.6 0.1 40
data sheet AD9121 rev. b | page 39 of 60 interpolation interpolation nco 1 0 ?1 cosine sine i data q data ftw[31:0] spectral inversion out_i out_q + ? nco phase offset [15:0] 09988-027 figure 56. digital quadrature modulator block diagram nco modulation the digital quadrature modulator makes use of a numerically controlled oscillator (nco), a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. a block diagram of the digital modulator is shown in figure 56. the fine modulation provided by the digital modulator, in conjunction with the coarse modu- lation of the interpolation filters and premodulation block, allows the signal to be placed anywhere in the output spectrum with very fine frequency resolution. the quadrature modulator is used to mix the carrier signal generated by the nco with the i and q signal. the nco produces a quadrature carrier signal to translate the input signal to a new center frequency. a complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90 from each other. the frequency of the complex carrier signal is set via ftw[31:0] in register 0x30 through register 0x33. the nco operating frequency, f nco , is at either f data (hb1 bypassed) or 2 f data (hb1 enabled). the frequency of the complex carrier signal can be set from dc up to f nco . the frequency tuning word (ftw) is calculated as 32 2 ?? nco carrier f f ftw the generated quadrature carrier signal is mixed with the i and q data. the quadrature products are then summed into the i and q datapaths, as shown in figure 56. updating the frequency tuning word the frequency tuning word registers are not updated immediately upon writing, as other configuration registers are. after loading the ftw registers with the desired values, bit 0 of register 0x36 must transition from 0 to 1 for the new ftw to take effect. datapath configuration configuring the AD9121 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. given these four parameters, the first step in configuring the datapath is to verify that the device supports the bandwidth requirements. the modes of the interpolation filters are then chosen. finally, any additional frequency offset requirements are determined and applied with premodulation and nco modulation. determining the datapath signal bandwidth the available signal bandwidth of the datapath is dependent on the center frequency of the output signal in relation to the center frequency of the interpolation filters used. signal center frequencies offset from the center frequencies of the half-band filters lower the available signal bandwidth. when correctly configured, the available complex signal band- width for 2 interpolation is always 80% of the input data rate. the available signal bandwidth for 4 interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in figure 57. note that in 4 interpolation mode, f dac = 4 f data ; therefore, the data shown in figure 57 repeats four times from dc to f dac . hb1 and hb2 hb2 and hb3 f out / f data bandwidth/ f data 0.2 0.8 0.5 0.3 0.4 0.6 0.8 1.0 09988-028 figure 57. signal bandwidth vs. center frequency of the output signal, 4 interpolation configuring 4 interpolation using the hb2 and hb3 filters can lower the power consumption of the device at the expense of band- width. the lower curve in figure 57 shows that the supported bandwidth in this mode varies from 30% to 50% of f data .
AD9121 data sheet rev. b | page 40 of 60 the available signal bandwidth for 8 interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in figure 58. note that in 8 interpolation mode, f dac = 8 f data ; therefore, the data shown in figure 58 repeats eight times from dc to f dac . hb1, hb2, and hb3 f out / f data bandwidth/ f data 0.25 0.8 0.6 0.5 1.00 0.75 0.50 0.1 0.9 0.6 0.4 09988-029 figure 58. signal bandwidth vs. center frequency of the output signal, 8 interpolation determining interpolation filter modes table 20 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, and signal modulation. the interpolation modes were chosen based on the final center frequency of the signal and by deter- mining the frequency shift of the signal required. when these parameters are known and put in terms of the input data rate (f data ), the filter configuration that comes closest to matching is selected from table 20. table 20. recommended interpolation filter mo des (register 0x1c through register 0x1e) filter modes interpolation factor hb1[1:0] hb2[5:0] hb3[5:0] f signal modulation f center shift 8 00 (mode 0) 000000 000000 dc 0 8 01 (mode 1) 001001 000000 dc 1 f data /2 8 2 10 (mode 2) 010010 001001 f data f data 8 11 (mode 3) 011011 001001 f data 1 3f data /2 8 00 (mode 0) 100100 010010 2f data 2f data 8 01 (mode 1) 101101 010010 2f data 1 5f data /2 8 10 (mode 2) 110110 011011 3f data 3f data 8 11 (mode 3) 111111 011011 3f data 1 7f data /2 8 00 (mode 0) 000000 100100 4f data 4f data 8 01 (mode 1) 001001 100100 4f data 1 9f data /2 8 10 (mode 2) 010010 101101 5f data 5f data 8 11 (mode 3) 011011 101101 5f data 1 11f data /2 8 00 (mode 0) 100100 110110 6f data 6f data 8 01 (mode 1) 101101 110110 6f data 1 13f data /2 8 10 (mode 2) 110110 111111 7f data 7f data 8 11 (mode 3) 111111 111111 7f data 1 15f data /2 4 00 (mode 0) 000000 bypass dc 0 4 3 01 (mode 1) 001001 bypass dc 1 f data /2 4 10 (mode 2) 010010 bypass f data f data 4 11 (mode 3) 011011 bypass f data 1 3f data /2 4 00 (mode 0) 100100 bypass 2f data 2f data 4 01 (mode 1) 101101 bypass 2f data 1 5f data /2 4 10 (mode 2) 110110 bypass 3f data 3f data 4 11 (mode 3) 111111 bypass 3f data 1 7f data /2 2 00 (mode 0) bypass bypass dc 0 2 01 (mode 1) bypass bypass dc 1 f data /2 2 10 (mode 2) bypass bypass f data f data 2 11 (mode 3) bypass bypass f data 1 3f data /2 1 when hb1 mode 1 or mode 3 is used, enabling premodulation provides an additional frequency translation of the input signal by f data /2, which centers a baseband input signal in the filter pass band. 2 this configuration was used in the 8 interpolation without nco example (see the 8 interp olation without nco section). 3 this configuration was used in the 4 interpolation wi th nco example (see the 4 i nterpolation with nco section).
data sheet AD9121 rev. b | page 41 of 60 datapath configuration examples 8 interpolation without nco for this example, the following parameters are given: ? f data = 100 msps ? 8 interpolation ? f bw = 75 mhz ? f center = 100 mhz the desired 75 mhz of bandwidth is 75% of f data . in this case, the ratio of f out /f data = 100/100 = 1.0. from figure 58, the band- width supported at f data is 0.8, which verifies that the AD9121 supports the bandwidth required in this configuration. the signal center frequency is f data and, assuming the input signal is at baseband, the frequency shift required is also f data . choosing the third row (highlighted by the superscripted number 2) of the interpolation factor column from table 20 selects filter modes that give a center frequency of f data and a frequency translation of f data . the selected modes for the three half-band filters are hb1, mode 2; hb2, mode 2; and hb3, mode 1. figure 59 shows how the signal propagates through the interpolation filters. because 2 f in1 = f in2 and 2 f in2 = f in3 , the signal appears frequency scaled by one-half into each consecutive stage. the output signal band spans 0.15 to 0.35 of f in3 (400 mhz). there- fore, the output frequency supported is 60 mhz to 140 mhz, which covers the 75 mhz bandwidth centered at 100 mhz, as desired. 4 interpolation with nco for this example, the following parameters are given: ? f data = 250 msps ? 4 interpolation ? f bw = 140 mhz ? f center = 175 mhz the desired 140 mhz of bandwidth is 56% of f data . as shown in figure 57, the value at 0.7 f data is 0.6. this is calculated as 0.8 ? 2(0.7 ? 0.6) = 0.6. this verifies that the AD9121 supports a bandwidth of 60% of f data , which exceeds the required 56%. the signal center frequency is 0.7 f data and, assuming the input signal is at baseband, the frequency shift required is also 0.7 f data . choosing the second row in the interpolation factor column in the 4 interpolation section of table 20 selects the filter modes that give a center frequency of f data /2 with no frequency translation. the selected modes for the three half-band filters are hb1, mode 1; hb2, mode 1; and hb3, bypassed. because mode 1 of hb1 was selected, the premodulation block should be enabled. this provides f data /2 modulation, which centers the baseband input data at the center frequency of hb1. the digital modulator can be used to provide the final frequency translation of 0.2 f data to place the output signal at 0.7 f data , as desired. the formula for calculating the ftw of the nco is as follows: 32 2 ?? nco carrier f f ftw where: f carrier = 0.2 f data . f nco = 2 f data . therefore, ftw = 2 32 /10. 0 1 2 3 0 ?0.5 0.5 hb1 0.1 0.4 0.6 1.5 2.0 f in1 1.0 0 ?0.5 0.5 hb3 0.2 ?0.2 0.3 0.7 0.15 0.35 1.5 2.0 f in3 1.0 0 7 5 3 4 0 6 2 1 ?0.5 0.5 hb2 0.25 0.75 0.3 0.7 1.25 1.75 1.5 2.0 f in2 1.0 0 7 5 3 6 4 0 1 2 09988-030 figure 59. signal propagation for 8 interpolation (f data modulation)
AD9121 data sheet rev. b | page 42 of 60 data rates vs . interpolation modes table 22 summarizes the maximum bus speed (f bus ) , supported input data rates , and signal bandwidths with the various combi - nations of bus width modes and interpolation rates . the real signal bandwidth supported is a fraction of the inpu t data rate , which depends on the interpolation filters (hb1, hb2, or hb3) selected . the complex signal bandwidth supported is twice the real signal bandwidth. in general, 2 interpolation is best supported by enabling hb1, and 4 interpolation is best sup ported by enabling hb1 and hb2 . however, i n some cases, power dissipation can be lowered by not using hb1 . if the bandwidth required is low enough, 2 interpo - lation c an be supported by using hb2 , and 4 interpolation can be supported by using hb2 and hb3. coarse modulation mi xing sequences the coarse digital quadrature modulation occurs within the interpolation filters. the modulation shifts the frequency spectrum of the incoming data by the frequency offset selected. the frequency offsets available are mu ltiples of the input data rate. the modulation is equivalent to multiplying the quadra - ture input signal by a complex carrier signal, c(t), of the form c ( t ) = cos( c t ) + j sin( c t ) in practice, this modulation results in the mixing functions shown in table 21. table 21 . modulation mixing sequences modulation mixing sequence f s /2 i = i, ? i, i, ? i, q = q, ? q, q, ? q, f s /4 i = i, q, ? i, ? q, q = q, ? i, ? q, i, 3 f s /4 i = i, ? q, ? i , q, q = q, i, ? q, ? i, f s /8 i = i, r(i + q), q, r( ? i + q), ? i, ? r(i + q), ? q, r(i ? q), q = q, r(q ? i), ? i, ? r(q + i), ? q, r( ? q + i), i, r(q + i), note that 2 2 = r as shown in table 21 , the mixing functions of most of the modes cross - couple samples between the i and q channels. the i and q channels operate independently only in f s /2 mode. this means that real modulation using both the i and q dac outputs can only be done in f s /2 mode . all other modulation modes require complex input data and produce complex output signals. table 22. summary of data rates and bandwidths vs . interpolation modes (dvdd18 , cvdd18 = 1. 9 v 2%) filter modes bus width hb 3 hb 2 hb 1 f bus (mbps) f data (mbps) real signal bandwidth (mhz) f dac (mhz) byte ( 8 bits) 0 0 0 1230 307.5 150 307.5 0 0 1 1230 307.5 120 615 0 1 0 1230 307.5 75 615 0 1 1 1230 307.5 120 1230 1 1 0 1230 307.5 75 1230 1 1 1 615 153.75 60 1230 word (1 4 bits) 0 0 0 1230 615 300 615 0 0 1 1000 5 00 200 1000 0 1 0 1230 615 150 1230 0 1 1 615 307.5 120 1230 1 1 0 615 307.5 75 1230 1 1 1 307.5 153.75 60 1230
data sheet AD9121 rev. b | page 43 of 60 quadrature phase cor rection the purpose of the quadrature phase correction block is to enable c ompensation of the phase imbalance of the analog quadrature modulator following the dac. if the quadrature modulator has a phase imbalance, the unwanted sideband appears with significant energy. tuning the quadrature phase adjust value can optimize image r ejection in single sideband radios . ordinarily , the i and q channels have an angle of precisely 90 between them. the quadrature phase adjustment is used to change the angle between the i and q channels. when i phase adj[9:0] (register 0x38 and register 0x 39) is set to 1000000000 , the i dac output moves approximately 1.75 away from the q dac output, creating an angle of 91.75 between the channels. when i phase adj[9:0] is set to 0111111111 , the i dac output moves approx - imately 1.75 toward the q dac outp ut, creating an angle of 88.25 between the channels . q phase adj[9:0] (register 0x3a and register 0x3b) works in a similar fashion . when q phase adj[9:0] is set to 1000000000, the q dac output moves approximately 1.75 away from the i dac output, creatin g an angle of 91.75 between the channels. when q phase adj[9:0] is set to 0111111111, the q dac output moves approximately 1.75 toward the i dac output, creating an angle of 88.25 between the channels . based on these two endpoints, the combined resoluti on of the phase compensation register is approximately 3.5 / 1024 or 0.00342 per code. dc offset correction the dc value of the i datapath and the q datapath can be independently controlled by adjusting the i dac offset[15:0] and q dac offset[15:0] values in register 0x3c th rough register 0x3f . these values are added directly to the datapath values. care should be taken not to overrange the transmitted values. figure 60 shows how the dac offset current varies as a f unction of the i dac offset[15:0] and q dac offset[15:0] values. with the digital inputs fixed at midscale (0x0000, twos complement data format), figure 60 shows the nominal i outxp and i out x n currents as the dac of fset value is swept from 0 to 65 , 535. because i out x p and i outxn are complementary current outputs, the sum of i outxp and i outxn is always 20 ma. 0x0000 0x4000 0x8000 0xc000 0xffff 5 10 15 20 5 10 15 20 0 0 dac offset v alue i outxn (ma) i outx p (ma) 09988-031 figure 60 . dac output currents vs. dac offset value inverse sinc filter the inverse sinc (sinc ? 1 ) filter is a nine - tap fir filter . the composite response of the sinc ? 1 filter and the sin(x)/x response of the dac is shown in figure 61 . the composite response has a pass - band ripple of less than 0.05 db up to a frequency of 0.4 f dacclk . to provide the necessary peaking at the upper end of the pass band, the inverse sinc filters shown have an intrinsic insertion loss of about 3.2 db . figure 61 shows the composite freq uency response. ?3.0 ?3.2 ?3.4 ?3.6 ?3.8 ?4.0 0 0.5 0.3 0.4 0.2 0.1 magnitude (db) f out / f dac 09988-032 figure 61 . sample composite responses of the sinc ? 1 filter with s i n(x)/x roll - off the sinc ? 1 filter is dis abled by default. it can be enabled by setting the bypass sinc ?1 bit to 0 ( register 0x1b, b it 6).
AD9121 data sheet rev. b | page 44 of 60 dac input clock conf igurations the AD9121 dac sampl ing clock (dacclk) can be sourced directly or by clock multiplying. clock multiplying use s the on - chip phase - locked loop (pll) , which accepts a reference clock operating at a submultiple of the desired dacclk rate, most commonly the data input frequency. the pll then multiplies the reference clock up to the desired dacclk frequency, which can then be used to generate all the internal clocks required by the dac . the clock multiplier provides a high quality clock that meets the performance requirements of most applications. using the on - chip clock multi plier eliminates the need to generate and distribute the high speed dacclk. the second mode bypasses the clock multiplier circuitry and allows the dacclk to be sourced directly to the dac core. this mode enables the user to source a very high quality clock directly to the dac core. sourcing the dacclk directly through the ref clk p, refclkn, dacclkp, and dacclk n pins may be necessary in demanding applications that require the lowest possible dac output noise, particularly when directly synthesizing signals ab ove 150 mhz. driving the dac clk and refclk input s the differential dac clk and refclk inputs share similar clock receiver input circuitry . figure 62 shows a simplified circuit diagram of the input s . the on - chip cloc k receiver has a differential input impedance of about 10 k? . it is self - biased to a common - mode voltage of about 1.25 v . the inputs can be driven by direct coupling differential pecl or lvds drivers . the inputs can also be ac - coupled if the driving source cannot meet the input compliance voltage of the receiver . 1.25v 5k? 5k? dacclk p , refclk p dacclkn, refclkn 09988-033 figure 62 . clock receiver input simplified equivalent circuit the minimum input drive level to either of the clock inputs is 1 00 mv p - p d ifferential . the optimal performance is achieved when the clock input signal is between 800 mv p - p d ifferential and 1.6 v p - p d ifferential . whether using the on - chip clock multiplier or sourcing the dacclk directly, it is necessary that the input clock signal to the device ha ve low jitter and fast edge rates to optimize the dac noise performa nce . direct clocking direct clocking with a low noise clock produces the lowest noise spectral density at the dac outputs. to select the differential clk inputs as the source for the dac sampling clock, set the pll e nable bit (register 0x 0a, bit 7 ) to 0 . t his power s down the internal pll clock multiplier and select s the input from the dac clk p and dacclkn pins as the source for the internal dac sampl ing clock . the device also has duty cycle correction circuitry and differ - ential input level correction circui try . enabling these circuits can provide improved performance in some cases . the control bits for these functions are in r egister 0x08 (s ee table 11 ) . clock multiplication the on - chip pll clock multipli cation circu it can be used to gen - erate the dac sampling clock from a lower frequency reference clock . when the pll e nable bit (register 0x0a , b it 7 ) is set to 1, the clock multiplication c ircuit generates the dac sampling clock from the lower rate refclk input . the f unctional diagram of the clock multiplier is shown in figure 63. the clock multiplication circuit operates such that the vco outputs a frequency, f vco , equal to the refclk input signal frequency multiplied by n1 n 0 . f vco = f refclk ( n1 n0 ) the dac sampl ing clock frequency, f dacclk , is equal to f dacclk = f refclk n1 the output frequency of the vco must be chosen to keep f vco in the optimal operating range of 1.0 ghz to 2.1 ghz . the frequency of the reference c lock and the values of n1 and n0 must be chosen so that the desired dacclk frequency can be synthesized and the vco output frequency is in the correct range. dacclkp/dacclkn (pin 2 and pin 3) adc vco loo p fi l ter refclkp/refclkn (pin 69 and pin 70) reg 0x0e[3:0] vco contro l volt age reg 0x0d[3:2] n0 reg 0x0d[1:0] n1 reg 0x06[7:6] pll lock lost pll locked phase detection reg 0x0a[7] pll enable reg 0x0d[7:6] n2 n2 dacclk pc_clk n1 n0 09988-034 figure 63 . pll clock multiplication circuit
data sheet AD9121 rev. b | page 45 of 60 pll settings th ree setti ngs for the pll circuitry should be programmed to their nominal values. the pll values shown in table 23 are the recommended settings for these parameters. table 23 . pll settings pll control register register address bit s optimal setting pll loop bandwidth [1:0] 0x0c [7: 6 ] 11 pll charge pump current [4:0] 0x0c [4:0] 1 0001 pll c ross - c ontrol e nable 0x0d 4 1 configuring the vco tuning band the pll vco has a valid operating range from approxim ately 1.0 ghz to 2.1 ghz covered in 63 overlapping frequency bands. for any desired vco output frequency, there may be several valid pll band select values. the frequency bands of a typical device are shown in figur e 64. device - to - device variations and operating temperature affect the actual band frequency range. therefore, it is required that the optimal pll band select value be determi ned for each individual device. 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 1000 2200 2000 1800 1600 1400 1200 pl l band vco frequenc y (mhz) 09988-035 figure 64 . pll l ock r ange o ver t emperature for a typical device automatic vco band select the device has an automatic vco band select feature on chip. using the automatic vco band select feature is a simple and reliable method of configuring the vco frequency band. this featur e is enabled by starting the pll in manual mode, and then placing the pll in auto band select mode. this is done by setting register 0x0a to a value of 0xcf, and then to a value of 0xa0. when these values are written, the device executes an automated routi ne that determines the optimal vco band setting for the device. the setting selected by the device ensures that the pll remains lock ed over the full ?40c to +85c operating temperature range of the device without further adjustment. (the pll remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes.) manual vco b and select the device also has a manual band select mode (pll manual enable, register 0x0a, bit 6 = 1) that allows the user to select the vco tuning band. i n manual mode, the vco band is set directly with the value written to the manual vco band bits (regi ster 0x0a, bit s [5:0]). to properly select the vco band, follow these steps: 1. put the device in manual band select mode by setting register 0x0a, bit 6 = 1. 2. sweep the vco band over a range of bands that result s in the pll being locked. 3. for each band , verify that the pll is locked and read the pll using the vco control voltage bits (register 0x0e , bits [3:0]). 4. select the band that results in the control voltage being clo sest to the center of the range, that is, 1 001 or 1000 (s ee table 24) . the resulting vco band should be the optimal setting for the device. write this value to the manual vco band bits (register 0x0a , bits [5:0]). 5. if desired, an indication of where the vco is within the operating frequency band can be dete rmined by querying the vco control voltage. table 24 shows how to interpret the pll vco control voltage value (register 0x0e, bits[ 3 :0]). table 24 . vco control voltage range indications vco control voltage (register 0x0e , bits[3:0] ) indication 1 111 move to higher vco b and 1 110 1 101 vco is operating in the higher end of the frequency band 1 100 1 011 1 010 1 001 vco is operating within an optimal region of the frequency band 1 000 0111 0110 0101 vco is operating in the lower end of the frequency band 0100 0011 0010 0001 move to lower vco b and 0000
AD9121 data sheet rev. b | page 46 of 60 analog outputs transmit dac operati on figure 65 shows a simplified block di agram of the transmit path dacs . the dac core consists of a current source array, a switch co re, digital control logic, and full - scale output current control. the dac full - scale output current (i fs ) is nominally 20 ma . the output currents from the i out 1 p /i out2p and i out 1 n / iout2n pins are complementary, meaning that the sum of the two currents always equals the full - scale current of the dac . the digital input code to the dac determines the effective differential current delivered to the load. i dac iout1 p iout1n q dac iout2n iout2 p current scaling i dac fs adjust register 0x40 q dac fs adjust register 0x44 0.1f 10k? r set fsadj refio 5k? 1.2v 09988-037 figure 65 . simplified block diagram of dac core the dac has a 1.2 v band gap reference with an output imped - ance of 5 k. the reference output voltage appears on the ref io pin. when using the internal reference, decouple the ref io pin to avss with a 0.1 f c apa ci to r. u se t he internal reference only for external circuits that draw dc currents of 2 a or less. for dyna mic loads or static loads greater than 2 a , buffer the ref io pin. if desired, the internal reference can be overdriven by applying an external reference ( from 1.10 v to 1.30 v) to the ref io pin. a 10 k external resistor, r set , must be connected from the fsadj pin to avss. this resistor, along with the reference control amplifier, sets up the correct internal bias currents for the dac. because the full - scale current is inversely proportional to this resistor, the tolerance of r set is reflected in the full - scale output amplitude. the full - scale current equation , where the dac gain is set indiv id - ually for the i and q dacs in r egister 0 x 40 and register 0 x 44, respectively , is as follows: u u dac gain r i set fs 16 3 72 v ref for the nominal values of v ref (1.2 v), r set (10 k), and dac g ain (512), the full - scale current of the dac is typically 20.16 ma. the dac full - scale current can be adjusted from 8.6 4 ma to 31.6 8 ma by setting the dac g ain parameter, as shown in figure 66. 35 0 0 1000 dac gain code i fs (ma) 30 25 20 15 10 5 200 400 600 800 09988-036 fi gure 66 . dac full - scale current vs. dac gain code transmit dac transfer function the output currents from the iout 1 p /iout2p and iout 1 n / iout2n pins are complementary, meaning that the sum of the two currents always equals the full - scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. iout1p/iout2p provide maxi - mum output current when all bits are high. the output currents vs . daccode for the dac outputs are e xpressed as fs n outxp i daccode i u 2 (1) outxp fs outxn i i i (2) where daccode = 0 to 2 n ? 1. transmit dac output configurations the optimum noise and distortion performance of the AD9121 is realized when it is configured for differential operation. the common - mode error sources of the dac outputs are significantly reduced by the common - mode rejection of a transformer or differential amplifier. these common - mode error sources include even - order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude incr eases. this is due to the first - order cancellation of various dynamic common - mode distortion mechanisms, digital feedthrough, an d noise.
data sheet AD9121 rev. b | page 47 of 60 figure 67 shows the most basic transmit dac output circuitry . a pair of resistors, r o , is used to convert each of the compl e - mentary output currents to a differential voltage output, v out . because the curr ent outputs of the dac are high impedance, the differential driving point impedance of the dac outputs, r out , is equal to 2 r o . figure 68 illustrates the output voltage waveforms . r o r o v i p + v in ? v outi iout1 p iout1n r o r o v q p + v qn ? v outq iout2 p iout2n 09988-038 figure 67 . basic transmit dac output circuit +v peak v cm 0 ?v peak v n v p v out 09988-039 figure 68 . o utput voltage waveforms the common - mode signal voltage, v cm , is calculated as o fs cm r i v = 2 the peak output voltage, v peak , is calculated as v peak = i fs r o with th is circuit configuration, the single - ended peak voltage is the same as the peak differential output voltage. transmit dac linear output signal swing to achieve optimum performance, t he dac outputs have a linear output compliance voltage range that must be adhered to . the linear output signal swing is dependent on the full - scale output current, i fs , and the common - mode level of the output . figure 69 and figure 70 show the im d performance vs . the output common - mode voltage at different full - scale currents and output frequencies. ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 imd (dbc) v cm (v) i fs = 20m a i fs = 10m a i fs = 30m a 09988-168 figure 69 . imd vs. output common - mode voltage (f out = 61 mhz, r l oa d = 50 ? d ifferential, i fs = 10 ma , 20 ma, and 30 ma) ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 imd (dbc) v cm (v) i fs = 20m a i fs = 10m a i fs = 30m a 09988-169 figure 70 . imd vs. output common - mode voltage (f out = 161 mhz, r l oa d = 50 ? d ifferential, i fs = 10 ma , 20 ma, and 30 ma) auxiliary dac operat ion the AD9121 has two auxiliary dacs : one associated with the i path and one associated with the q path . these auxiliary dacs can be used to compensate for dc offsets in the transmitted signal . each auxiliary dac has a single - ended current that can sink or source current into either the positi ve (p) or negative (n) output of the associated transmit dac . the auxiliary dac structure is shown in figure 71. iout1 p iout1n i dac v b i aux dac current direction i aux dac[9:0] i aux dac sign 09988-040 figure 71 . auxiliary dac structure
AD9121 data sheet rev. b | page 48 of 60 the control registers for the i and q a uxiliary dacs are r egister 0x4 2, register 0x43, register 0x4 6 , and register 0x47 . interfacing to modul ators the AD9121 interfaces to the adl537x family of modulators with a minimal number of components. an exam ple of the recommended interface circuitry is shown in figure 72. rbi p 50? rbin 50? 67 66 ibbn ibb p AD9121 adl537x rbqn 50? rbq p 50? 59 58 rli 100? rlq 100? iout1n iout1 p iout2 p iout2n qbb p qbbn 09988-041 figure 72 . typical interface circuitry between the AD9121 and t he adl537x f amily of modulators the baseband inputs of the adl537x family require a dc bias of 500 mv. the nominal midscale output current on each output of the dac is 10 ma (one - half the full - scale current). therefore, a single 50 ? resistor to ground from each of the dac outputs results in the desired 500 mv dc common - mode bias for the inputs to the adl537x . the signal level can be reduced through the addition of the load res istor in parallel with the modulator inputs. the peak - to - peak voltage swing of the transmitted signal is ) 2 ( ) 2 ( l b l b fs signal r r r r i v u u u u baseband filter impl ementation most applications require a baseband anti - imaging filter between the dac and the modulator to fi lter out nyquist images and broadband dac noise. the filter can be inserted between the i - v resistors a t the dac output and the signal level setting resistor across the modulator input. t his establishes the input and output impedances for the filter. figure 74 shows a fifth - order, low - pass filter. a common - mode choke is used between the i - v resistors and the remainder of the filter. this removes the common - mode signal produced by the dac and prevents the common - mod e signal from being converted to a differential signal, which can appear as unwanted spurious signals in the output spectrum. splitting the first filter capacitor into two and grounding the center point creates a common - mode low - pass filter, providing addi tional common - mode rejection of high frequency signals. a purely differential filter can pass common - mode signals. driving the adl5375 - 15 the adl5375 - 15 req uires a 1500 mv dc bias and, therefore, requires a slightly more complex interface than most other analog devices modul ators. it is necessary to level - shift the dac output from a 500 mv dc bias to the 1500 mv dc bias required by the adl5375 - 15 . level - shifting can be achieved with a purely passive network, as shown in figure 73 . in this network, the dc bias of the dac remains at 500 mv , wh ereas the input to the adl5375 - 15 is 1500 mv. this passive, level - shifting network introduces approximately 2 db of loss in the ac signal. 67 66 ibbn ibb p AD9121 adl5375-15 59 58 21 22 9 10 rbi p 45.3? rbin 45.3? rbqn 45.3? rbq p 45.3? rli p 3480? rlin 3480? rlqn 3480? rlq p 3480? iout1n iout1 p iout2 p iout2n qbb p qbbn rsi p 1k? rsin 1k? rsqn 1k? rsq p 1k? 5v 5v 09988-043 figure 73 . passive, level - shifting netwo rk for biasing the adl5375 - 15 AD9121 50? 50? 33nh 33nh 2pf 56nh 56nh 140? 6pf 3pf 3pf 22pf 22pf adl537x 09988-042 figure 74 . dac modulator interface with fifth - order, low - pass filter
data sheet AD9121 rev. b | page 49 of 60 reducing lo leakage and unwanted sidebands analog quadrature m odulators can introduce unwanted signals at the lo frequency due to dc offset voltages in the i and q baseband inputs , as well as feedth rough paths from the lo input to the out - put . the lo feedthrough can be nulled by applying the correct dc offset voltages at the dac output . this can be done us ing the a uxiliary dacs (reg ister 0x42, register 0x43, register 0x46, and register 0x47) or by using the digital dc offset adjustments (reg ister 0x3c th rough register 0x3f) . the advantage of u sing the a uxiliary dacs is that none of the main dac dynamic ran ge is u s ed to perform the dc offset adjustment . the disadvantage is that the common - mode level of the output signal change s as a function of the a ux iliary dac current . the opposite is true when the digital o ffset adjustment is used. good sideband suppress ion requires both gain and phase matching of the i and q signals . the i/q phase adjust registers (reg ister 0x38 th rough register 0x3b) and the dac fs a djust registers (reg ister 0x40 and register 0x44 ) can be used to calibrate the i and q transmit paths to optimize sideband suppression .
AD9121 data sheet rev. b | page 50 of 60 device power management power dissipation the AD9121 has four supply rails : avdd33, iovdd, dvdd18 , and cvdd18. the avdd33 supply powers the dac core circuitry . the power dissipation of the avdd33 supply rail is independent of the digital operating mode and sample rate. the current drawn from the avdd33 supply rail is typically 5 5 ma (18 2 mw) when the full - scale current of the i and q dacs is set to the nominal value of 20 ma. changing the full - scale current directly affects the supply current drawn from the avdd33 rail. for example, if the full - scale current of the i dac and the q dac is changed to 10 ma, the avdd33 supply current drops by 20 ma to 3 5 ma. the iovdd voltage supplies the serial port i/o pins, the reset pin , and the irq pin . the voltage applied to the iovdd pin can range from 1.8 v to 3.3 v . the current drawn by the iovdd supply pin is typically 3 ma. the dvdd18 supply powers all of the digital signal processing blocks of the device . the power consumption from this supply is a function of which digital blocks are enabled and the frequency at which the device is operating. the cvdd18 supply powers the clock receiver and clock distri - bution circuitry . the power consumption from t his supply varies directly with the operating frequency of the device. cvdd18 also powers the pll . the power dissipation of the pll is typically 80 m w when enabled. figure 75 through figure 79 show the power dissipation of the AD9121 under a variety of operating conditions. all of the graphs were taken with data being supplied to both the i and q dac s. the power consumption of the device does not vary significantly with ch anges in the coarse modulation mode selected or the analog output frequency. figure 75 through figure 79 show t he total power dissipation , as well as the power dissipation of the dvdd18 and cvdd18 supplie s. maximum power dissipation can be estimated to be 20% higher than the typical power dissipation. 1700 1500 1300 1 100 900 700 500 300 100 0 300 250 200 150 100 50 f d at a (mhz) power (mw) 1 interpol a tion 2 interpol a tion 4 interpol a tion 8 interpol a tion 09988-044 figure 75 . total power dissipation vs. f data w ith out pll, fine nco, or inverse sinc 1200 1000 800 600 400 200 0 0 300 250 200 150 100 50 f d at a (mhz) power (mw) 1 interpol a tion 2 interpol a tion 4 interpol a tion 8 interpol a tion 09988-045 figure 76 . dvdd 18 power dissipation vs. f data w ith out fine nco or inverse sinc 250 200 150 100 50 0 0 300 250 200 150 100 50 f d at a (mhz) power (mw) 1 interpol a tion 2 interpol a tion 4 interpol a tion 8 interpol a tion 09988-046 figure 77 . cvdd18 power dissipation vs. f data with pll d isabled
data sheet AD9121 rev. b | page 51 of 60 300 250 200 150 100 50 0 0 1200 1000 800 600 400 200 f dac (mhz) power (mw) 09988-047 figure 78 . dvdd18 power dissipation vs. f dac d ue to inverse sinc filter 300 250 200 150 100 50 0 50 300 250 200 150 100 f d at a (mhz) power (mw) 1 interpol a tion 2, 4, 8 interpol a tion 09988-048 figure 79 . dvdd18 power dissipation vs. f data d ue to fine nco temperature sensor the AD9121 has a band gap temperature sensor for m onito ring the temperatur e chang e of the AD9121 . the temperature must be calibra t ed against a kno wn temper ature to remove the part - to - part var iation on the band gap circuit used to sense the temperature. the dacclk must be running at a minimum of 100 mhz to obtain a reliable temperature measurement. t o monitor temperature change , the user must take a reading at a known a m bient temperature f or a single - point calibration of each AD9121 device . tx = t ref + 7.7 ( code_x ? code_ref )/1000 + 1 w here : code_x is the readback code at the unknown temperature , tx . code_ref is the readback code at the calibrated temperature , t ref . to use the temperature sensor, it must be enabled by setting reg ister 0x01, b it 4 , to 0. in addition , to obtain accurate read - ings, the die temperature range control register ( register 0x48) should be set to 0x02.
AD9121 data sheet rev. b | page 52 of 60 multichip synchroniz ation system demands may require that the outputs of multiple dacs be synchronized with each other or with a system clo ck . systems that support transmit diversity or beam forming, where multiple antennas are used to transmit a correlated signal , require multiple dac outputs to be phase aligned with each other . systems with a time division multiplexing transmit chain may r eq uire one or more dacs to be synchronized with a system - level reference clock. multiple devices are considered synchronized to each other when the state of the clock generation state machines is identical for all parts and when time - aligned data is being re ad from the fifos of all parts simultaneously. devices are considered synchronized to a system clock when there is a fixed and known relationship between the clock generation state machine and the data being read from the fifo and a particular clock edge o f the system clock . the AD9121 has provisions for enabling multiple devices to be synchronized to each other or to a system clock . the AD9121 supports synchronization in two different modes : data rate mode and fifo rate mode . in data rate mode , the input d ata rate represents the lowest synchronized clock rate . in fifo rate mode , the fifo rate, which is the data rate divided by the fifo depth of 8, represents the lowest rate clock . the advantage of fifo rate synchronization is increased time between the setu p and hold time windows for dci changes relative to the dacclk or refclk input . when the synchro - nization state machine is on in data rate mode, the elasticity of the fifo is not used to absorb timing variations between the data source and the dac, resulti ng in setup and hold time wi n dows repeating at the input data rate . the method chosen for providing the dac sampling clock directly affe cts the synchronization methods available . when the device clock multiplier is used, only data rate mode is available . w hen the dac sampling clock is sourced directly, both data rate mode and fifo rate mode synchronization are available . the following sections de scribe the synchronization methods for enabling both clocking modes and querying the status of the synchronizatio n logic. the full synchronization methods described are used to align mu ltiple dual dacs within one dac clk cycle. to achieve syn - chronization within one dacclk cycle , both the refclk and frame signals are required to perform back - end and front - end alignmen t. if synchronization does not need to be this accurate, other options can be used. in data rate mode or in fifo rate mode , using soft align ment of the fifo for multiple dacs synchronize s the dac outputs within two data clock cycles (see the serial port initiated fifo reset section). for more information about synchronization , see the an - 1093 application note, synchro - nization of multiple ad9122 txdac+ converters . synchr onization with clock multiplication when using the clock multiplier to generate the dac sample rate clock, the refclk input signal acts as both the reference clock for the pll - based clock multiplier and the synchronization signal . t o synchronize devices, d istribute the refclk signal with low skew to all the devices that need to be synchronized . skew between the refclk signals of the different devices show s up directly as a timing mismatch at the dac outputs . because two clocks are shared on the same signal , an appro - priate frequency must be chosen for the synchronization and refclk signal s. the frame and dci signals can be created in the fpga along with the data . a circuit diagram of a typical configuration is shown in figure 80. system clock low skew clock driver m a tched length traces refclkp/ refclkn framep/ framen dcip/ dcin refclkp/ refclkn framep/ framen dcip/ dcin iout1p/ iout1n iout2p/ iout2n fpg a 09988-049 figure 80 . typical circuit diagram for synchronizing devices the procedure for synchronization when using the pll section outlines the steps required to synchronize multiple devices . the p rocedure assumes that the refclk signal is applied to all the devices and that the pll of each device is phase locked to it . the procedure must be carried out on each individual device. procedure for s ynchronization w hen u sing the pll in the initialization of the AD9121 , all the clock signals (dac clk , dci, frame, synchronization , and refclk) must be present and stable before the synchronization feature is turned on. configure the AD9121 for periodic data rate synchronization by writing 0xc8 to the sync cont rol register (r egister 0x10) . additional synchronization options are available (see the additional synchronization features section) . read the sync status register (r egister 0x12) to verify that the sync l ocked bi t ( b it 6) is set high , indicating that the device achieved back - end synchronization , and that the sync l ost bit ( b it 7) is low . these levels indicate that the clocks are running with a constant and known phase relative to the synchroniza - tion signal . reset the fifo by strobing the frame signal high for the time interval required to write two complete input data words . resetting the fifo ensures that the correct data is being read from the fifo. this completes the synchronization procedure ; all devices shoul d now be synchronized.
data sheet AD9121 rev. b | page 53 of 60 refclkp(1)/ refclkn(1) refclkp(2)/ refclkn(2) dcip(2)/ dcin(2) framep(2)/ framen(2) t skew t sdci t hdci 09988-050 figure 81 . timing diagram r equired for synchronizing devices dacclkp/ dacclkn framep/ framen refclkp/ refclkn dcip/ dcin iout1p/ iout1n dcip/ dcin dacclkp/ dacclkn refclkp/ refclkn framep/ framen iout2p/ iout2n sample r a te clock low skew clock driver sync clock low skew clock driver m a tched length traces fpg a 09988-051 figure 82 . typical circuit diagram for synchronizing devices to a system clock to maintain synchronization, the ske w between the refclk signals of the devices must be less than t skew ns . when resetting the fifo, the fram e signal must be held high for the time interval required to write two complete input data words. a timing diagram of the input signals is shown in figure 81. figure 81 shows a re f clk frequency equal to the data rate . although this is the most common situation, it is not strictly required for proper synchronization . any refclk frequency that satisfies the following equation is acceptable . (this equation is valid only when the pll is used because only data rate mode is available with the pll on .) f sync_ i = f dacclk /2 n and f sync_ i f data where n = 0, 1, 2, or 3. as an example, a configurati on with 4 interpolation and clock frequencies of f vco = 1600 mhz, f dacclk = 800 mhz, f d ata = 200 mhz, and f sync_i = 100 mhz is a viable solution. synchronization with direct clocking when directly sourcing the dac sample rate clock, a separate refclk inpu t signal is required for synchronization . t o syn - chronize devices, the dac clk signal and the refclk signal must be distributed with low skew to all the devices being synchronized . if the devices need to be synchronized to a master clock, use the master clo ck directly for generating the refclk input (see figure 82) . data rate mode synch ronization the procedure for data rate synchronization when directly sourcing the dac sampling clock sectio n outlines the steps required to synchronize multiple devices in data rate mode . the procedure assumes that the dac clk and refclk signals are applied to all the devices . the procedure must be carried out on each individual device. procedure for data rate s ynchronization w hen d irectly s ourcing the dac sampling clock configure the AD9121 for periodic data rate synchronization by writing 0xc 8 to the sync control register (r egister 0x10) . additional synchronization options are available (see the additional synchronization features section ). read the sync l ocked bit (register 0x12, b it 6) to verify that the device is back - end synchronized . a high level on this bit indicates that the clocks are running with a constant and known phase relative to the synchronization signal . reset the fifo by strobing the fram e signal high for one complete dci period . resetting the fifo ensures that the correct data is being read from the fifo of each of the devices simultaneously.
AD9121 data sheet rev. b | page 54 of 60 correct data is being read from the fifo of each of the devices simultaneously. this completes the synchronization procedure; all devices should now be synchronized. to ensure that each dac is updated with the correct data on the same clk edge, two timing relationships must be met on each dac. ? dcip/dcin and d[15:0]p/d[15:0]n must meet the setup and hold times with respect to the rising edge of dacclk. ? synchronization (refclk) must also meet the setup and hold times with respect to the rising edge of dacclk. when these conditions are met, the outputs of the dacs are updated within one dac clock cycle of each other. the timing requirements of the input signals are shown in figure 83. dacclkp(1)/ dacclkn(1) dacclkp(2)/ dacclkn(2) refclkp(2)/ refclkn(2) dcip(2)/ dcin(2) framep(2)/ framen(2) t skew t susync t sdci t hdci t hsync 09988-052 figure 83. data rate synchronizat ion signal timing requirements, 2 interpolation figure 83 shows the synchronization signal timing with 2 interpolation; therefore, f dci = ? f clk . the refclk input is shown to be equal to the data rate. the maximum frequency at which the device can be resynchronized in data rate mode can be expressed as f sync_i = f data /2 n where n is any non-negative integer. generally, for values of n greater than or equal to 3, select the fifo rate synchronization mode. when synchronization is used in data rate mode, the timing constraint between the dci and dacclk must be met according to table 25. in data rate mode, the allowed phase drift between the dci and dacclk is limited to one dci cycle. the dci to dacclk timing restriction is required to prevent corruption of the data transfer when the fifo is constantly reset. the required timing between the dci and dacclk is shown in figure 84. table 25. dci to dacclk setup and hold times dci delay register 0x16, bits[1:0] minimum setup time, t sdci (ns) minimum hold time, t hdci (ns) sampling interval (ns) 00 ?0.07 0.82 0.75 01 ?0.24 1.13 0.89 10 ?0.39 1.40 1.01 11 ?0.49 1.55 1.06 dci dacclk/ refclk t data t sdci t hdci sampling interval 09988-147 figure 84. timing diagram for input data port (data rate mode) fifo rate mode synchronization the procedure for fifo rate synchronization when directly sourcing the dac sampling clock section outlines the steps required to synchronize multiple devices in fifo rate mode. the procedure assumes that the dacclk and refclk signals are applied to all the devices. the procedure must be carried out on each individual device. procedure for fifo rate synchronization when directly sourcing the dac sampling clock configure the AD9121 for periodic fifo rate synchronization by writing 0x88 to the sync control register (register 0x10). addi- tional synchronization options are available (see the additional synchronization features section). read the sync locked bit (register 0x12, bit 6) to verify that the device is back-end synchronized. a high level on this bit indicates that the clocks are running with a constant and known phase relative to the synchronization signal. reset the fifo by strobing the frame signal high for one com- plete dci period. resetting the fifo ensures that the correct data is being read from the fifo of each of the devices simultaneously. this completes the synchronization procedure; all devices should now be synchronized. when these conditions are met, the outputs of the dacs are updated within one dac clock cycle of each other. the timing requirements of the input signals are shown in figure 85. dacclkp(1)/ dacclkn(1) dacclkp(2)/ dacclkn(2) refclkp(2)/ refclkn(2) dcip(2)/ dcin(2) framep(2)/ framen(2) t skew t susync t hsync 09988-053 figure 85. fifo rate synchronizat ion signal timing requirements, 2 interpolation
data sheet AD9121 rev. b | page 55 of 60 figure 85 shows the synchronization signal timing with 2 interpolation ; therefore, f dci = ? f clk . the refclk input is shown to be e qual to the fifo rate . t he maximum frequency at which the device can be resynchronized in fifo rate mode can be expressed as f sync_ i = f data / ( 8 2 n ) where n is any non - negative integer. additional synchroni zation features table 26 shows the required timing between the dacclk and the synchronization clock when synchronization is used . this timing restriction applies to both data rate mode and fifo rate mode. table 26 . synchronization setup a nd hold times parameter min max unit t skew ?t dacclk /2 +t dacclk /2 ps t s u sync 100 ps t h sync 330 ps one - time synchronization when implementing the full multichip synchronization feature ( with the refclk and frame signals align ed within one dacclk cycle ), the user may experience difficulty meeting the dacclk to synchronization clock timing . in this case, a one - time synchroni - zation method can be used. before im plementing the one - time synchro nization , make sure th at the synchronization signal is locked by checking both the sync signal lock ed and the sync signal lost flags ( b it 4 and bit 5 in r egister 0x06 ) . it is also important that synchronization not be enable d before stable ref clk signals are present from the fpga or asic. for m ore information and a d etailed flowchart of the one - time synchronizati on feature , see the an - 1093 application note, synchronization of multiple ad912 2 txdac+ converters . sync status bits when th e sync locked bit (register 0x12, bit 6) is set, it indicates that the synchronizatio n logic has reached alignment . this align - ment is determined when the clock generation state machine phase is constant . alignment take s from (11 + a veraging) 64 to (11 + a ve ragin g) 128 dacclk cycles . th e sync locked bit can also trig ger an irq , as described in the interrupt request operation section. when th e sync lost bit (register 0x12, bit 7) is set, it indicates that a previously synchronized device has lost alignment . this bit is latched a nd remain s set until cleared by overwriting the register . this bit can also trigger an irq , as described in the interrupt request operation section. the sync phase readback bits (r egister 0x13, b i ts [ 7:0 ] ) r eport the current clock phase in a 6.2 format . bits [ 7:2 ] report which of the 64 states (0 to 63) the clock is currently in . when averag ing is enabled, b its [ 1:0 ] provide ? state accuracy (for 0, ?, ?, ?) . the lower two bits give an indication of t he timing margin issues that may exist . if the synchronization sampling is error free, the fractional clock state should be 00. timing optimization the synchronization signal (refclk) is sampled by a version of the dacclk . if sampling errors are detected, the opposite sampling edge can be selected to improve the sampling point . the sampling edge can be selected by setting r egister 0x10, b it 3 (1 = rising and 0 = falling) . the synchronization logic resynchronize s when a phase change between the synchronizat ion signal (refclk) and the state of the clock generation state machine exceeds a threshold . to mitigate the effects of jitter and prevent erroneous resynchronizations, the relative phase can be averaged . the amount of averaging is set by the sync averagin g bits (r egister 0x10, b its [ 2:0 ] ) and can be set from 1 to 128 . the higher the number of averages, the more slowly the device recognize s and resynchronize s to a legitimate phase correction . generally , the averaging should be mad e as large as possible while still meet ing the allotted resynchroniza - tion time interval. note that , if the average synchronization sampling result is in approximately the middle of the probability curve, the synchronization engine can be unstable, resulting in corrupted output. the value of the sync phase request[5:0] bits (register 0x11, bits[5:0]) is the state to which the clock generation state machine resets upon initialization. by varying this value, the timing of the internal clocks, with respect to the synchronization signal ( refclk) , can be adjusted. every increment of the sync phase request[5:0] value advances the internal clocks by one dacclk cycle. this offset can be used for two purposes: to skew the out - puts of two synchronized dac outputs in increments of the dacclk cycl e, and to change the relative timing between the dac output and the sync input (refclk) . this may allow for a more optimal placement of the dci sampling point in data rate synchronization mode.
AD9121 data sheet rev. b | page 56 of 60 interrupt request op eration the AD9121 provides an inte r rupt request output signal on p in 7 ( irq ) that can be used to notify an external host processor of significant device events . upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. the irq pin is an open - drain, active low output. pull t he irq pin high external to the device. this pin can be tied to the interrupt pins of other devices with open - drain outputs to wire - or these pins together. the event fl ags provide visibility into the device . these flags are located in the two event flag registers, register 0x06 and register 0x07 . the behavior of each event flag is independently selected in the interrupt enable registers , register 0x04 and register 0x05 . when the flag interrupt enable is active, the event flag latche s and trigger s an external interrupt . when the flag interrupt is disabled, the event flag monitors the source signal, but the irq pin remain s inactive. figure 86 shows the irq - related circuitry and how the event flag signals propagate to the irq output . the interrupt _ enable signal represents one bit from the interrupt enable register . the event _ flag _ source signal represents one bit from the event flag register . the event_flag_source signal represents one of the device signals that can be monitored , such as the pll_ locked signal from the pll phase detector or the fifo _warning_ 1 signal from the fifo con troller. when an interrupt enable bit is set high, the corresponding event flag bit reflects a positively tripped version of the event_flag_source signal; that is, the event flag bit is latched on the rising edge of the event_flag_source signal. this signa l also asserts the external irq pin. when an interrupt enable bit is set low, the event flag bit reflect s the current status of the event_flag_source signal , and the event flag ha s no effect on the external irq pin. the latched version of an event flag (the interrupt _ source signal) can be cleared in two ways . the recommended way is by writing 1 to the corresponding event flag bit . a hardware or soft - ware reset also clear s the interrupt_source signal. interrupt service ro utine interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. th e events that require host action should be enabled so that the host is notified when they occur. for events requiring host interv en tion upon irq activation, run the following routine to clear an interrupt request: 1. read the status of the event flag bits that are being monitored. 2. set the inte r rupt enable bit low so that the unlatched event_flag_source signal can be monitored directly. 3. perform any actions that may be required to clear the event_flag_source . in many cases, no specific actions may be required. 4. read the event flag to verify th at th e actions taken have clear ed the event_flag_source . 5. clear the interrupt by writing 1 to the event flag bit. 6. set the inter r upt enable bits of the events to be monitored. note that some event_flag_source signals are latched signals. these signals are cleared by writing to the correspon d - ing event flag bit. for more information abo ut each event flag , see register 0x06 and register 0x07 in table 11 . interrupt_enable event_flag_source device_reset event_flag interrupt_ source 1 0 other interrupt sources irq write_1_ t o_event_flag 09988-054 figure 86 . simplified schematic of irq circuitry
data sheet AD9121 rev. b | page 57 of 60 interface timing val idation the AD9121 provid es on - chip sample error detection (sed) circuitry that simplifies verification of the input data interface . the sed circuitry compares the input data samples captured at the digital input pins with a set of comparison values . the comparison values are loa ded into registers th rough the spi port . differences between the captured values and the compar - ison values are detected and stored . options are available for customizing sed test sequencing and error handling. sed operation the sed circuitry operates on a data set made up of four 14- bit input words , denoted as i0, q0, i1, and q1 . to properly align the i nput samples, the first i data - word ( that is, i0 ) is indicated by as serting fram e for at least one complete input sample . figure 87 shows the input timing of the interface in word mode . the fram e signal can be issued once at the start of the data transmission , or it can be asserted repeatedly at intervals coi nciding with the i 0 and q0 data - words. frame d at a[13:0] q1 q0 i0 i1 i0 q0 09988-056 figure 87 . timing diagram of e xtended fram e signal required to align input data for sed the sed has three flag bits (register 0x67, b it 5 , bit 1, and bit 0 ) that indicate the results of the input sample com parisons . the sample error detected bit ( register 0x67, b it 5) is set when an error is detected and remain s set until cleared . the sed also provides registers that indicate which input data bits experienced errors (register 0x70 th rough register 0x73) . the se bits are latched and indicate the accumulated errors detected until cleared. autosample error detection ( aed ) is an autoclear function in the sed. the auto clear mode has two effects : it activates the compare fail bit and the compare pass bit (register 0 x67, b it 1 and bit 0) and changes the behavior of r egister 0x70 th rough register 0x73 . the compare pass bit is set if the last comparison indicated th at th e sample was error free . the c ompare f ail bit i s s et if an error is detected . the compare fail bit is automatically cleared by the reception of eight consecutive error - free compar - i sons . when auto clear mode is enabled, r egister 0x70 th rough register 0x73 accumulate errors as previously described but are reset to all 0 s after eight consecutive error - free s ample comparisons are made . if desired, t he sample error detected , compare pass , and com - pare fail flags can be configured to trigger the irq pin when active . this is done by enabling the appropriate bits in the event flag register (r egis ter 0x07). table 27 shows a progression of the input sample comparison results and the corresponding states of the error flags. table 27. progression of input sample comparison result s and the resulting sed register values compare result s (pass/fail) p f f f p p p p p p p p p f p f reg ister 0x67, bit 5 (sample error detected) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 register 0x67, bit 1 (comp ar e fai l ) 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 register 0x6 7, bit 0 (comp ar e pass) 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 register 0x70 to register 0x73 (errors detected x_bits[15:0]) z 1 n 2 n 2 n 2 n 2 n 2 n 2 n 2 n 2 n 2 n 2 n 2 z 1 n 2 n 2 n 2 1 z = all 0s. 2 n = nonzero.
AD9121 data sheet rev. b | page 58 of 60 sed example normal operation the following example illu strates the sed configuration for continuously monitoring the input data and assertion of the irq pin when a single error is detected. 1. load the following comparison values. (comparison values can be chosen arbitrarily; however, choosing v alues that require frequent bit toggling provides the most robust test.) register 0x68: i0[7:0] register 0x69: i0[15:8] register 0x6a: q0[7:0] register 0x6b: q0[15:8] register 0x6c: i1[7:0] register 0x6d: i1[15:8] register 0x6e: q1[7:0] register 0x6f: q1[1 5:8] 2. enable the sed error detect flag to assert the irq pin. (set register 0x05 to 0x04.) 3. begin transmitting the input data pattern. 4. write to register 0x67 to enable the sed. (set register 0x67 to 0x80.) 5. clear the sed errors in register 0x67 and register 0x07. when the sed is first turned on, the frame signal may be detected immediately; therefore, the sed failure bit may be asserted due to the unknown initial frame status. for this reason, the sed compare fail status bit must be cleared at least once immediately after enabling the sed. if irq is asserted, read register 0x67 and register 0x70 through register 0x73 to verify that a sed error was detected and to deter - mine which input bits were in error. the bits in registe r 0x70 through register 0x73 are latched; therefore, the bits indicate any errors that occurred on those bits throughout the test ( not only the errors that caused the error detected flag to be set ) . note that the frame signal is not required during normal operation when the device is configured for word mode. enabling the alignment of the i0 sample as described in the sed operation section requires the use of the frame signal. the timing diagram for byte mode is the same as during normal operation and is shown in figure 43.
data sheet AD9121 rev. b | page 59 of 60 example start - up routine t o ensure reliable start - up of the AD9121 , certain sequences should be followed . this section sh ows an example start - up routine . this example uses the configuration described in the device configuration section . device configuration the following device configu ration is used for this example: ? f d ata = 122.88 msps ? interpolation is 4, using hb1 = 10 and hb2 = 010010 ? input data is baseband data ? f out = 140 mhz ? f refclk = 122.88 mhz ? pll is enabled ? fine nco is enabled ? inverse sinc filter is enabled ? synchronization is enabled ? silicon revision is r2 derived pll settings the following pll settings can be derive d fro m the device configuration: ? f dacclk = f d ata interpolation = 491.52 mhz ? f vco = 4 f dacclk = 1966.08 mhz (1 ghz < f vco < 2 ghz) ? n1 = f dacclk /f refclk = 4 ? n2 = f vco /f dacclk = 4 derived nco settings the following nco settings can be derived from the device c onfiguration: ? f nco = 2 f d ata ? f carrier = f out ? f modhb1 = 140 ? 122.88 = 17.12 mhz ? ftw = 17.12/(2 122.8) 2 32 = 0x11d55555 start - up sequence the following sequence configure s the power clock and register write sequenci ng for reliable device start - up in pll on mode : power up device (no specific power supply sequence is required) apply stable refclk input signal. apply stable dci input signal. issue h/w reset (optional). device configuration register write sequence: 0x00 ? 0x2 0 /* issue software reset */ 0x00 ? 0x00 /* start pll */ 0x0d ? 0xd9 0x0a ? 0xc0 0x0a ? 0x8 0 /* verify pll is locked */ read 0x0e /* expect bit 7 = 1 */ /* configure interpolation filters */ 0x1b ? 0x84 0x1c ? 0x04 0x1d ? 0x24 /* configure nco */ 0x1e ? 0x01 0x30 ? 0x55 0x31 ? 0x55 0x32 ? 0xd5 0x33 ? 0x11 /* update frequenc y tuning word */ 0x36 ? 0x01 0x36 ? 0x00 /* choose data rate mode */ 0x10 ? 0x48 /* issue software fifo reset */ 0x17 ? 0x04 0x18 ? 0x02 /* verify fifo reset */ read 0x18 /* expect 0x07 */ 0x18 ? 0x00 read 0x19 /* expect 0x1f or 0x0f or 0x07 */
AD9121 data sheet rev. b | page 60 of 60 outline dimensions compliant to jedec standards mo-220-vnnd-4 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref pin 1 indicator seating plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indicator coplanarity 0.08 06-25-2012-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pa d bottom view 10.10 10.00 sq 9.90 9.85 9.75 sq 9.65 0.25 min 6.15 6.00 sq 5.85 figure 88. 72-lead lead frame chip scale package [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp-72-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9121bcpz ?40c to +85c 72-lead lfcsp_vq cp-72-7 AD9121bcpzrl ?40c to +85c 72-lead lfcsp_vq cp-72-7 AD9121-m5372-ebz evaluation board connected to adl5372 modulator AD9121-m5375-ebz evaluation board connected to adl5375 modulator 1 z = rohs compliant part. ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09988-0-10/12(b)

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